ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 33

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Table 6.
5,3
Bit
4
2
1
0
CC register description
Bit name
I1, I0
H
N
C
Z
Interrupt management bits - interrupt
Arithmetic management bit - Half carry
Arithmetic management bit - Negative
Arithmetic management bit - Zero
Arithmetic management bit - Carry/borrow
The combination of the I1 and I0 bits gives the current interrupt
software priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (= interrupt disable)
These two bits are set/cleared by hardware when entering in
interrupt. The loaded value is given by the corresponding bits in the
interrupt software priority registers (IxSPR). They can be also
set/cleared by software with the RIM, SIM, IRET, HALT, WFI and
PUSH/POP instructions. See
This bit is set by hardware when a carry occurs between bits 3 and 4
of the ALU during an ADD or ADC instructions. It is reset by
hardware during the same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is
useful in BCD arithmetic subroutines.
This bit is set and cleared by hardware. It is representative of the
result sign of the last arithmetic, logical or data manipulation. It’s a
copy of the result 7
0: The result of the last operation is positive or null
1: The result of the last operation is negative (i.e. the most significant
bit is a logic 1)
This bit is accessed by the JRMI and JRPL instructions.
This bit is set and cleared by hardware. This bit indicates that the
result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero
1: The result of the last operation is zero
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an
overflow or an underflow has occurred during the last arithmetic
operation.
0: No overflow or underflow has occurred
1: An overflow or underflow has occurred
This bit is driven by the SCF and RCF instructions and tested by the
JRC and JRNC instructions. It is also affected by the ‘bit test and
branch’, shift and rotate instructions.
th
bit.
Function
Section 7: Interrupts
Central processing unit
for more details.
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