ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 199

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
15.2
15.2.1
15.2.2
I/O port A and F configuration
External clock source with PLL
ROM devices only
When using an external quartz crystal or ceramic resonator, a few f
be lost when the signal pattern in
device to enter test mode and return to user mode after a few clock periods. User program
execution and I/O status are not changed, only a few clock cycles are lost.
This happens with either one of the following configurations (see also
PA3 = 0, PF4 = 1, PF1 = 0 while PLL option is disabled and PF0 is toggling.
PA3 = 0, PF4 = 1, PF1 = 0, PF0 = 1 while PLL option is enabled.
Table 108. Port A and F configuration
As a consequence, for cycle-accurate operations, these configurations are prohibited in
either input or output mode.
Workaround
To avoid this occurring, it is recommended to connect one of these pins to GND (PF4 or
PF0) or V
PLL is not supported with external clock source.
OFF
PLL
ON
DD
PA3
(PA3 or PF1).
0
0
PF4
1
1
PF1
0
0
Table 108
Toggling
PF0
1
occurs . This is because this pattern causes the
Max. 2 clock cycles lost at each rising or
falling edge of PF0
Max. 1 clock cycle lost out of every 16
Clock disturbance
OSC2
Table
Known limitations
clock periods may
108):
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