ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 105

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
Figure 47. Single master/single slave application
Slave select management
As an alternative to using the SS pin to control the slave select signal, the application can
choose to manage the slave select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In master mode:
●
In slave mode:
There are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on 2nd clock edge):
●
If CPHA = 0 (data latched on 1st clock edge):
●
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V
managing the SS function by software (SSM = 1 and SSI = 0 in the in the SPICSR
register)
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a write
collision error occurs when the slave writes to the shift register (see
(WCOL) on page
MSbit
generator
SPI clock
8-bit shift register
Master
110).
LSbit
Figure
49)
MISO
MOSI
SCK
SS
+5V
MISO
MOSI
SCK
SS
SS
, or made free for standard I/O by
MSbit
Not used if SS is managed by software
8-bit shift register
On-chip peripherals
Slave
Write collision error
Figure
LSbit
48):
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