ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 197

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
15.1.5
15.1.6
Nested interrupt context
The symptom does not occur when the interrupts are handled normally, i.e. when:
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If these conditions are not met, the symptom can be avoided by implementing the following
sequence:
16-bit timer PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
TIMD set simultaneously with OC interrupt
Description
If the 16-bit timer is disabled at the same time as the output compare event occurs, then the
output compare flag gets locked and cannot be cleared before the timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the output compare flag cannot be cleared in the
timer interrupt routine. Consequently the interrupt service routine is called repeatedly and
the application gets stuck which causes the watchdog reset if enabled by the application.
Workaround
Disable the timer interrupt before disabling the timer. While enabling, first enable the timer,
then the timer interrupts.
Perform the following to disable the timer:
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Perform the following to enable the timer again:
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The interrupt flag is cleared within its own interrupt routine
The interrupt flag is cleared within any interrupt routine with higher or identical priority
leve
The interrupt flag is cleared in any part of the code while this interrupt is disabled
PUSH CC
SIM
Reset interrupt flag
POP CC
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
TACSR & or TBCSR & = ~0x40; // Enable the timer
TACR1 or TBCR1 = 0x40; // Enable the compare interrup
Known limitations
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