ST7232AK2-Auto STMicroelectronics, ST7232AK2-Auto Datasheet - Page 57

• Manufacturer Part Number: ST7232AK2-Auto
• Description: 8-bit MCU for automotive, 16 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMicroelectronics

Specifications of ST7232AK2-Auto

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and bypass for external clock
• Four Power Saving Modes: halt, active halt, wait and slow
• Main Clock Controller With: real time base, beep and clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST7232Axx-Auto
8.4.1
Note:
Caution:
Active halt mode
Active halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the main clock
controller status register (MCCSR) is set (see
time clock and beeper (MCC/RTC) on page 73
The MCU can exit active halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see
mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure
When entering active halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In active halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in active halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering active halt mode while the watchdog is active does not generate a reset. This
means that the device cannot spend more than a defined delay in this power saving mode.
When exiting active halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before t
on option byte). Otherwise, the ST7 enters halt mode for the remaining t
Figure 22. Active halt timing overview
1. This delay occurs only if the MCU exits active halt mode by means of a reset
23).
Table 15: Interrupt mapping on page
DELAY
after the interrupt occurs (t
[MCCSR.OIE = 1]
Run
instruction
HALT
Active
halt
256 OR 4096 CPU
Reset or interrupt
cycle delay
Section 10.2: Main clock controller with real-
for more details on the MCCSR register).
DELAY
(1)
53) or a reset. When exiting active halt
= 256 or 4096 t
Fetch
vector
Run
Power saving modes
CPU
DELAY
delay depending
period.
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