BSP-15 Equator Technologies, BSP-15 Datasheet - Page 13

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BSP-15

Manufacturer Part Number
BSP-15
Description
Broadband Signal Processor
Manufacturer
Equator Technologies
Datasheet

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Chapter 1
1.1 Overview
The Equator BSP™-15 processor is the latest member of the Equator Broadband Signal Processor
family offering highly integrated single chip solutions for broadband products such as set-top
boxes, digital televisions, video conferencing systems, medical imaging products, digital video
editing equipment, and office automation products.
The processing power of the BSP-15 processor combined with iMMediaTools
environment and library of audio and video codecs provide a proven and effective solution for
building rapidly evolving broadband solutions.
1.1.1 Features
The Equator BSP-15 processor provides the following features:
September 6, 2002
Advanced four-issue, super pipelined Very Long Instruction Word Processor
The VLIW processor provides four integer ALUs, two 64-bit SIMD ALUs, and two 128-bit
SIMD ALUs. The processor has 32 1-bit predicate registers, eight 128-bit registers, and 128
32-bit registers, which can be paired into 64-bit registers.
Advanced high throughput memory hierarchy
Instructions are provided to the VLIW processor by a 32 KB two-way set-associative instruc-
tion cache with an LRU replacement policy. Instructions are stored in compressed format. Data
is provided to the processor by a 32 KB four-way set associative, four-bank interleaved data
cache with an LRU replacement policy. Memory protection is provided by separate instruction,
data and DMA MMUs, each with a fully set-associative 16 entry TLB. Off chip memory is con-
nected via a glueless high speed 64-bit SDRAM/SGRAM interface supporting up to 128 MB of
external memory.
Specialized coprocessors
Variable length encoding and decoding is handled by the VLx coprocessor with 4 KB instruc-
tion and 4 KB data memory. The Video Filter coprocessor provides up to 4 vertical tap and 5
horizontal tap filtering, aided by a 6 KB line buffer. High data throughput is provided by the
DataStreamer™, a programmable 64 channel DMA controller with 8 KB of buffering . The
Display Refresh Controller provides color space conversion, palette table lookup and hardware
cursor functionality. A DES coprocessor accelerates DES encryption and decryption.
Introduction
HWR.BSP15.DS.REV.H
BSP-15 Processor Datasheet
code generation
1

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