BSP-15 Equator Technologies, BSP-15 Datasheet - Page 27

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

2.7.2.2 ITU-656 Input Interface
2.7.2.3 ITU-656 Output Interface
2.7.2.4 General Purpose Data Port (GPDP)
2.7.3 Display Refresh Controller
2.7.4 Analog RGB
September 6, 2002
used in conjunction with the Program Clock References embedded in the transport stream to track the
timing reference. This is accomplished by using a software loop filter to implement a 1-bit sigma-delta
modulator to provide a controlling voltage for the external VCXO that drives pclk . The sigma-delta
data stream is output at 1.5 MHz on the tci_vdac pin via the primary TCI.
In addition to the local clock counters, there is a programmable 27 MHz timer in each TCI module that
generates an interrupt on overflow (rollover).
This interface provides direct connection to an ITU-R BT.601/656 format NTSC/PAL video input
decoder. The external decoder can be controlled using the IIC Serial Bus.
A glueless interface to a NTSC/PAL video encoder is provided, enabling the BSP-15 DSP to directly
generate high-quality NTSC or PAL video-output signals. This interface supports 8-bit 525 and 625 line
resolutions with either separate H/Vsync (ITU-R BT. 601) or inline sync (ITU-R BT.656). Advanced
video post-filtering on the BSP-15 DSP via software can produce flicker-free output when converting
interlace-to-progressive output. The external NTSC/PAL encoder can be controlled using the IIC Serial
Bus.
The general purpose data port provides an 8-bit parallel input/output port. Together with a clock and a
couple of handshake signals, this provides an alternative I/O port than just PCI for multiple MAP chips
to communicate at higher inter-chip bandwidths. The GDPD data bandwidth supported is up to 60MB/s
depending upon other system activity.
Sophisticated video blending, 2D graphics with alpha blending, PIP, and hardware cursor overlays for
EPGs (Electronic Program Guides) and navigation services have been designed into the Display Refresh
Controller. Color space conversion, Gamma correction, and choice of YCbCr or RGB output format is
supported.
The BSP-15 processor provides an analog RGB interfacing supporting resolutions up to 1280x1024.
The BSP-15 DSP’s RGB DACs (digital-to-analog converters) are part of the Display Refresh Controller
block. The 8-bit DACs allow pixel clock rates up to 110 MHz. The BSP-15 DSP generates RS-343A
compatible monitor signals into doubly-terminated 75
monitors.
The full scale output level is determined by an external reference voltage V
resistor R
The DACs output the three primary analog color signals – red video, green video and blue video – with
the video sync information superimposed on the green video output. Also, separate hsync and vsync
reference signals are provided.
nominal
= 1117 . The full scale level can be adjusted by adjusting the resistor value.
HWR.BSP15.DS.REV.H
load and is capable of driving standard SVGA
ref
BSP-15 Processor Datasheet
at 1.235V and an external
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