BSP-15 Equator Technologies, BSP-15 Datasheet - Page 18

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

6
2.1 The VLIW Core
2.1.1 Execution Units
BSP-15 Processor Datasheet
These I/O functions execute in parallel with the CPU and eliminate the need for several external ASICs
with their associated cost and bandwidth issues.
A glueless 64-bit wide SDRAM interface connects the BSP-15 processor to external memory with a
maximum size of 128 MB. The BSP-15 DSP supports a 128 MB maximum memory size. A 32-bit
33/66 MHz PCI bus interface is also supported. The BSP-15 DSP boots from either the PCI bus or the
Flash ROM interface.
There are three on-chip PLLs (core/SDRAM, pixel, audio) that generate all the internal clocks from a
single 27 MHz external clock input ( pclk ). The tci_vdac pin can be used to output a controlling
signal that can be used to drive a one bit sigma-delta modulator for an external VCXO which in turns
modulates the frequency on pclk .
Real-time processing of multimedia data stresses processor performance, I/O performance and memory
performance. There are three basic ways to increase a processor’s performance: decrease the cycle time,
decrease the number of cycles required to execute an instruction, and execute more instructions per
cycle. The first two are becoming increasingly difficult to improve beyond process scheduling, while the
last (executing more instructions per cycle) is now receiving more attention. Executing more
instructions per cycle exploits the natural parallelism available in most software routines. Very Long
Instruction Word (VLIW) processors use this parallelism by packing multiple operations into a single
instruction word, which is then executed as a unit.
VLIW architectures differ from superscalar architectures in that the grouping and scheduling of
instructions for execution is done at compile time, rather than execution time. The compiler searches for
eligible operations, checks for dependencies and resource conflicts, and packages these eligible
operations into VLIW instructions. The VLIW compiler can explore beyond the limited search window
seen in superscalar architectures and cross natural boundaries, such as branches, to search for
opportunities for enhanced parallelism. The Equator compiler uses a technique known as “trace
scheduling” to search a whole routine for eligible operations.
By moving the difficult task of finding parallelism into software, VLIW compiler techniques
dramatically simplify the CPU design by reducing gate count and freeing valuable die area for other
performance enhancements or lower chip costs. While VLIW is primarily designed to exploit
parallelism, its simplification of the processor architecture allows for reduced cycle times as well.
The BSP-15 DSP operations are primarily three-operand RISC operations. As in any typical RISC
architecture, load and store operations are the only means of referencing memory. The BSP-15 DSP has
four functional units: two I-ALUs and two IG-ALUs. Each I-ALU contains a load-store unit, an integer
ALU, and a branch unit. Each IG-ALU contains an integer/graphics unit and a multimedia operation
unit. The I-ALU and IG-ALU support different operations, but many integer and logical operations are
implemented in both units. This overlap allows the compiler to schedule more operations in parallel and
make more efficient use of all the functional units.
There are 128 32-bit registers usable separately or in pairs as 64-bit registers, 32 1-bit predicate
registers, and eight special 128-bit registers for the VLIW core CPU. These 128-bit (PLC/PLV) registers
are used for FIR filter, SAD, FFT, ADD, DCT, and other specialized partitioned integer operations. The
large register files help minimize unnecessary instruction dependencies caused by logically distinct
register reuses.
Each BSP-15 DSP instruction contains four operations per cycle. The Media Intrinsics instructions
include partitioned operations over these media data types. Load and store operations can perform one,
two, four, and eight byte accesses, with support for both little-endian and big-endian byte orderings.
HWR.BSP15.DS.REV.H
September 6, 2002