BSP-15 Equator Technologies, BSP-15 Datasheet - Page 40

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

28
BSP-15 Processor Datasheet
Table 4-3 PCI interface signals
pci_req#[2:0]
pci_gnt#[2:0]
Signal
pci_devsel#
pci_frame#
pci_trdy#
pci_irdy#
pci_stop#
pci_inta#
pci_idsel
pci_rst#
pci_par
pci_clk
Pins
# of
1
1
1
1
1
1
1
1
1
1
3
3
B (od)
I/O
B
B
B
B
B
B
B
B
I
I
I
The initiator ready signal is asserted when the PCI master is ready for a data
transaction. The PCI bus master must monitor the pci_devsel_ signal line to
NOTE:
signal is an interrupt request input from PCI devices. The BSP-15 DSP sees
during configuration read and write transactions. This signal is inactive in a
BSP-15 DSP core, etc. are reset by the assertion of this signal. PCI pad cell
When the BSP-15 DSP is not designated as the PCI bus “HOST”, then this
interrupt on the PCI bus. The BSP-15 DSP pad cell does not contain a pull
The initialization device select is used as a slot addressed chip select input
pci_stop_ is asserted by the target to request the master to stop the current
The assertion of pci_req_ in a non-self-hosted configuration indicates that
address on the pci_ad[31:0] bus and will participate in (claim) the current
determine if a target bus has claimed the transaction or if it will execute a
signal is the open drain output generating an asynchronous level sensitive
A single parity bit is calculated over pci_ad[31:0], and pci_c_be[3:0] and
edge of pci_rst_. pci_devsel_ remains tri-stated until driven by the target.
pci_clk provides timing for all PCI transactions on the PCI bus. All other
drivers are disabled by the assertion of this signal, as specified in the PCI
The assertion of pci_gnt_ in a non-self-hosted environment indicates that
The target ready signal is asserted when the PCI target is ready for a data
Master Abort termination. pci_devsel_ will be tri-stated from the leading
This signal indicates a reset of all PCI resources. In addition, the internal
A target asserts the pci_devsel_ signal line to indicate it has decoded the
Transaction framing for PCI transfers. The initial assertion indicates the
Description
When the BSP-15 DSP is designated as the PCI bus “HOST” then this
address phase and the start of a PCI transaction. Continued assertion
PCI signals are sampled on the rising edge of pci_clk, and all timing
HWR.BSP15.DS.REV.H
the BSP-15 DSP has been granted the use of the PCI bus.
The BSP-15 DSP’s core clock PLL does not use this clock
as a core PLL reference clock.
parameters are defined with respect to this edge.
the BSP-15 DSP desires the use of the PCI bus.
determines the burst size of the transaction.
transferred over this signal.
and utilizes this interrupt.
self-hosted configuration.
up for this signal.
2.1 document.
transaction.
transfer.
transfer.
September 6, 2002