BSP-15 Equator Technologies, BSP-15 Datasheet - Page 63

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

September 6, 2002
the SDRAM components. They should be adjusted so that setup and hold requirements of both the
SDRAM and the BSP-15 DSP are met.
Table 6-7 SDRAM interface timing parameters
a.
b. f
c.
d. sdrtnclk is used as the reference clock.
e.
f
t
t
t
t
Symbol
os
oh
ds
dh
sdram
Measured with SdMrckDly = 0 and SdMckDly = 3.
The center of the rising edges of sdclk1 and sdclk2 is used as the reference point.
A matching mechanism is provided to compensate for the propagation delay through circuit board traces to
and from the external SDRAM devices. To optimize read timing margin, sdrtnclk should be connected to
sdclk with a dedicated trace, with an optional lumped RC load attached to the middle, to account for the
number of SDRAM devices attached to the clock line.
d, e
c
c, d
sdram
b
= 1 / t
sdram
sdclk frequency
Output setup time for address, data, control (sdcs#,
sdras#, sdcas#, sdwe#, sddqm)
Output hold time of address, data, control (sdcs_,
sdras_, sdcas_, sdwe_, sddqm)
Input data setup time
Input data hold time
Description
HWR.BSP15.DS.REV.H
a
Min
1.5
1.5
2
2
-
BSP-15 Processor Datasheet
Max
135
-
-
-
-
Unit
MHz
ns
ns
ns
ns
51