BSP-15 Equator Technologies, BSP-15 Datasheet - Page 71

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

6.4.7 ITU-R BT.601/656 interface timing
September 6, 2002
Table 6-16 ITU-R BT.601/656 input interface timing parameters
f
t
t
h
s
ntsc_in
Symbol
Figure 6.10 ITU-R BT.601/656 input timing measurement
Figure 6.11 ITU-R BT.601/656 output timing measurement
ntsc_ina_clk27
ntsc_ina_hsync
ntsc_ina_vsync
ntsc_ina_data[7:0]
This timing diagram and table include information for the primary video input port. The
primary video input bus
horizontal sync (bit 8), and vertical sync (bit 9). The secondary video input signals have
identical timing relationships
ntsc_out_data[7:0]
ntsc_out_hsync
ntsc_out_vsync
pclk
NTSC input clock frequency
Input hold time for video_ina[9:0], from cross over of rising
clock
Input setup time video_ina[9:0], to the cross over of rising
clock
Description
video_ina[9:0]
t
pclk
HWR.BSP15.DS.REV.H
t
s
t
h
t
includes the byte-wide data bus (bits 7:0),
delay
t
ntsc_in
t
hold
Min
1
5
-
BSP-15 Processor Datasheet
Max
-
-
Unit
MHz
ns
ns
59