BSP-15 Equator Technologies, BSP-15 Datasheet - Page 70

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

58
6.4.6 Transport Channel Interface timing
BSP-15 Processor Datasheet
Table 6-15 TCI timing parameters
a.
b. In serial mode, it is required that t
c.
d. For correct video clock counter operation, f
f
t
t
h
s
tci
Symbol
Figure 6.9 TCI timing measurement conditions
In parallel mode, it is required that t
For correct audio clock counter operation, f
produced by the on-chip PLL.
tci_data
tci_enable
tci_err_
tci_clk
tci_sync
The timing diagram and
relationships, input setup, and hold times are identical for the secondary TCI input port.
However, the
video_ina[9:0]
tci_err_
TCI clock frequency
Hold time
Setup time
(bit 9)
Description
tci_vdac
t
includes
s
t
Table 6-15
h
output is not present on the secondary output port. Inputs
core
a, b, c, d
core
tci_data[7:0]
> ½ f
HWR.BSP15.DS.REV.H
> f
tci_clk
tci_clk
core
core
are relevant to the primary TCI input port. Timing
/f
.
video
.
/f
audio
> 4, where f
t
tci
> 4, where f
(bits 7:0),
Min
video
1
4
-
audio
is the frequency of pclk.
tci_enable
is the frequency of audioclk_out
Max
27 (parallel)
80 (serial)
-
-
(bit 8), and
September 6, 2002
Unit
MHz
ns
ns