BSP-15 Equator Technologies, BSP-15 Datasheet - Page 39

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

4.4 SDRAM
The
in
BSP-15
4.5 PCI Bus
The
September 6, 2002
Table
Table 4-2 Memory interface signals
Table 4-3 PCI interface signals
BSP-15
BSP-15
pci_ad[31:0]
pci_cbe[3:0]
Signal
Signal
sdclk, sdclk1,
sddata[63:0]
DSP supports DRAM widths of 8-bit, 16-bit or 32-bits.
sdadr[13:0]
sddqm[7:0]
sdcs_[3:0]
4-2. The
sdrtnclk
TOTAL
sdcas#
sdras#
sdwe#
sdclk2
DSP supports either a SDRAM or SGRAM memory system using the signals shown
DSP provides the PCI bus as the primary system interface. 4-3 lists the PCI signals.
BSP-15
Pins
# of
32
4
Pins
# of
14
64
97
DSP supports a memory system of 64-bit or 32-bit data width. The
4
1
1
1
8
3
1
I/O
B
B
I/O
O
O
O
O
O
O
O
B
I
For PCI cycles, the bus command and byte enables are used to transfer the
PCI command during the address phase and are used to transfer byte lane
pci_frame_ is first asserted. Data is transferred on this bus in subsequent
Description
DSP. These are also input mask bits for Write-per-Bit. When block write
sdrtnclk is driven by sdclk. This signal is used for latching the data from
Chip Select signal lines indicate that the command on the output lines is
for each memory chip. If this signal is high, the output command(s) will
Address lines indicate row addresses when sdras_ is active and indicate
Data Input/Output lines transfer data between the memory and BSP-15
PCI multiplexed address and data lines. The address is driven when
clock. All SDRAM/SGRAM input signals are sampled on the positive
HWR.BSP15.DS.REV.H
Description
sdclk, sdclk1, and sdclk2 are driven by the BSP-15 DSP’s SDRAM
SDRAM/SGRAM. During write, sddqm = 1 prevents a write to the
sdcas_ is part of the output command to the SDRAM/SGRAM
sdras_ is part of the output command to the SDRAM/SGRAM
During read, sddqm = 1 turns off the output buffers of
is activated, these lines provide column address mask
Write enable (sdwe_) is part of the output command
be ignored by each corresponding memory chip
enables during subsequent data phases.
column addresses when sdcas_ is active
current memory location
SDRAM/SGRAM
edge of sdclk
clocks.
BSP-15 Processor Datasheet
27