BSP-15 Equator Technologies, BSP-15 Datasheet - Page 74

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

62
6.4.10 dRGB timing
BSP-15 Processor Datasheet
Table 6-20 IIC interface timing parameters
a.
b. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
c.
The BSP-15 generates all dRGB data signals on the rising edge of the pixelclk_out clock output.
An external device should latch the dRGB data with the falling edge of pixelclk_out .
f
t
t
t
t
t
t
t
t
t
t
C
hd_sta
low
high
su_sta
hd_dat
su_dat
r
f
su_sto
buf
sck
b
Symbol
Figure 6.15 dRGB timing diagram
All values referred to V
the SCL signal) to bridge the undefined region of the falling edge of SCL.
C
b
= total capacitance of one bus line in pF.
a
pixelclk_out
dRGB(23:0)
iic_sck clock frequency.
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
LOW period of the iic_sck clock.
HIGH period of the iic_sck clock.
Setup time for a repeated START
condition.
Data hold time.
Data setup time.
Rise time of both iic_sda and
iic_sck signals.
Fall time of both iic_sda and
iic_sck signals.
Setup time for STOP condition.
Bus free time between a STOP
and START condition.
Capacitive load for each bus line.
Description
IHmin
and V
ILmax
HWR.BSP15.DS.REV.H
dRGB(n)
levels. See
Standard Mode
Min
250
2.3
4.7
4.0
4.7
4.0
4.7
0
0
-
-
-
Table
b
6-4.
dRGB(n + 1)
Max
1000
3.45
100
300
400
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast Mode
Min
0.57
1.27
250
0.6
0.6
0.6
1.3
0
0
-
b
dRGB(n + 2)
b
b
c
Max
400
300
300
400
September 6, 2002
0.9
-
-
-
-
-
-
-
Unit
IHmin
kHz
pF
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
of