BSP-15 Equator Technologies, BSP-15 Datasheet - Page 38

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

26
4.2 Legend
4.3 Processor Clock
There is a single 27 MHz reference clock signal for generating internal clocks.
BSP-15 Processor Datasheet
A........................................... analog signal
B........................................... bi-directional
I ............................................ input
O........................................... output
od.......................................... open drain or active pull down
trailing “#” ........................... active low
()........................................... parentheses indicate number of shared signal pins
Table 4-1 Processor clock signal description
audioclk_byp_in
pixelclk_byp_in
coreclk_byp_in
Signal
sdclk_byp_in
(coreclk_out)
audioclk_out
pixelclk_out
tcia_vdac
pclk_out
TOTAL
pclk
Pins
# of
1
1
1
1
1
1
1
1
1
9
I/O
O
O
O
O
I
I
I
I
I
27 MHz VCXO input that serves as the reference signal to the three on-chip
Sigma-delta output from software loop filter for controlling external VCXO
PLLs. It is also a reference clock for the video output and the IIC interface
Transmit clock for GPDP (xmt_clk) or PLL-bypass input for pixel clock
Description
HWR.BSP15.DS.REV.H
Audio clock output used for IIS interface master MCLK
Bypass input for the SDRAM clock.
Bypass input for the audio clock.
Bypass input for the core clock
Output for the pixel clock.
Output for the core clock.
for pclk
September 6, 2002