BSP-15 Equator Technologies, BSP-15 Datasheet - Page 37

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

Chapter 4
4.1 Interface Summary
September 6, 2002
(rom_addr[19]/rom_addr[21]/rom_addr[1])/
ntsc_out_hsync / xmt_req
(rom_addr[18]/rom_addr[20]/rom_addr[0])/
ntsc_out_vsync / rcv_ack
<reset_strap[7:0]>/
(rom_addr[9:2]/rom_addr[17:10]/rom_data[7:0])/
ntsc_out_data[7:0] / xmt_data_out[7:0]
Figure 4.1 BSP-15 Interface
(rom_oe#)/iis_out_data[2]
(rom_wrt#)/iis_out_data[1]
(rom_ale)/iis_out_data[0]
rom_cs#
pclk
coreclk_byp_in
pixelclk_byp_in / xmt_clk
audioclk_out
tcia_vdac
sdclk_byp_in
audioclk_byp_in
pclk_out
pixelclk_ou
pci_ad[31:0]
pci_cbe[3:0]
pci_frame#
pci_trdy#
pci_irdy#
pci_stop#
pci_par
pci_devsel#
pci_clk
pci_rst#
pci_inta#
pci_idsel
pci_req#[2:0]
pci_gnt#[2:0]
pci_serr_intb#
pci_pme#
iis_in_data
iis_in_lr
iis_in_bclk
iis_out_lr
iis_out_bclk
Signal Descriptions
HWR.BSP15.DS.REV.H
Processor
Output
Clock
(PLL)
Video
ROM
Flash
PCI
IIS
BSP-15
Controller
SDRAM
Video
Input
chip
IEC958
(DRC)
JTAG
CRT
IIC
sdadr[13:0]
sddata[63:0]
sdcs[3:0]#
sdras#
sdcas#
sdwe#
sddqm[7:0]
sdclk
sdclk1
sdclk2
sdrtnclk
iic_sda
iic_sck
iic_select
vsync
hsync
gdac_fscale
gdac_comp
gdac_blue
gdac_green
gdac_red
tcia_inuse
tcia_sync
tcia_clk
tcia_err# / ntsc_ina_vsync / xmt_ack
tcia_enable / ntsc_ina_hsync / rcv_req
tcia_data[7:0] / ntsc_ina_data[7:0] / rcv_data_in[7:0]
ntsc_ina_clk27 / rcv_clk
tcib_inuse
tcib_sync
tcib_clk
tcib_err# / ntsc_inb_vsync
tcib_enable / ntsc_inb_hsync
tcib_data[7:0] / ntsc_inb_data[7:0]
ntsc_inb_clk27
iec958_in
iec958_out
tck
tms
tdi
tdo
trst
( ) --- valid during boot-up
< > --- valid during reset
# --- active low signal
BSP-15 Processor Datasheet
25