BSP-15 Equator Technologies, BSP-15 Datasheet - Page 28

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

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2.7.5 Digital RGB
2.7.6 IIC Interface Unit
2.7.7 ROM Controller
BSP-15 Processor Datasheet
The BSP-15 processor provides a digital RGB interface that connects gluelessly to an active matrix flat
panel display using a pixel depth of 12, 18, or 24 bits.
The Inter-IC (IIC) serial bus was originally developed by Philips to facilitate communications and
control among integrated circuits in consumer electronics. Using this two-wire serial interface, the
BSP-15 DSP can function as a master or slave device to relay status and control information to external
devices.
The IIC interface unit has an additional output signal, iic_select that allows BSP-15 DSP’s
software to control an external analog multiplexer/level converter that can switch between a regular IIC
bus and any other external bus (such as DDC for a monitor interface). This signal can also be used as a
general purpose output.
The ROM Controller (ROMCON) unit performs four distinct functions.
The purpose of the Configuration/Boot Sequencer is to control the boot up process of the chip. During
reset, the resistor straps connected to the ntsc_out_data[7:0] pins are examined to determine
how BSP-15 DSP will configure itself and boot. If the resistor straps indicate to boot from ROM, the
Boot Sequencer directs the Flash ROM Interface Controller to transfer bytes from the external ROM
device to the BSP-15 DSP’s configuration registers and to the PCI configuration registers. The 6KB line
buffer memory of the Video Filter is then used to store the bootstrap program for system boot up.
ROMCON copies the next 6 KB from ROM into the Video Filter memory (VfMem) through an 8-bit
configuration bus. After the boot code has been loaded, ROMCON unstalls (restarts) the VLIW core,
which in turn begins to execute the boot code out of VfMem. The ROMCON unit operates at 27 MHz
during the configuration loading, since the core PLL cannot be programmed to be taken out of bypass
mode until after the VLIW core has been unstalled.
Alternatively, for booting via the PCI interface, ROMCON plays a mostly passive role. In this case, an
external host loads the VfMem with boot code and initiates boot of the VLIW core via a PIO write to
unstall the VLIW core.
ROMCON also runs power-on diagnostics during the boot and may be paused at various points for
status testing. ROMCON requires minimal chip resources so that standard power-on diagnostics can run
without having to bring up all portions of the chip, allowing the chip to be tested in more manageable
stages.
• The Chip Configuration and ROM Boot Sequencer is a state machine for reading chip configura-
• The Flash ROM Interface controls the actual reading and writing of an off-chip flash ROM
• The Interrupt Controller/Collector provides a means for enabling, setting, and clearing hardware
• The PLL I/O provides PIO access to the programmable registers related to the various on-chip
tion and boot code at system startup.
device.
and software interrupts to the VLIW core and PCI bus controller.
PLLs. The three PLLs for the core/SDRAM, pixel, and audio clocks are programmed indirectly
via PIO registers within the ROMCON unit.
HWR.BSP15.DS.REV.H
September 6, 2002