BSP-15 Equator Technologies, BSP-15 Datasheet - Page 24

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

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2.5.2 Data Transfer Switch (DTS)
2.5.3 DataStreamer DMA Controller
2.5.4 PCI Bus
BSP-15 Processor Datasheet
The DTS is a split-transaction bus. The DTS contains the data and address buses, a high speed bridging
system, and a bus arbiter. The bridge, arbiter, and bus arrangement is a very high-speed communication
solution that allows multiple media applications to be executed concurrently.
The arbiter can handle multiple requestors using priority based scheduling.
The DataStreamer DMA controller is a high performance, programmable DMA engine that performs
buffered data transfer between different BSP-15 DSP memory subsystems or between memories and I/O
devices. The DataStreamer DMA controller is programmed and controlled by software. The
DataStreamer DMA controller then performs the requested transfer without further intervention from
the core.
The DataStreamer DMA controller can perform the following classes of transfers:
The DataStreamer DMA controller features include:
The PCI unit implements a 32-bit PCI 2.1 interface with speed up to 66 MHz. The PCI interface is a
single function device with two BARs. Certain fields in the configuration registers may be initialized on
power-up through ROM control. As a PCI target, the PCI interface allows access to the BSP-15 DSP’s
SDRAM (coherently or non-coherently with respect to the Data Cache). The PCI interface also allows
access to several programmer-visible control registers, PIO space and SDRAM. As a PCI master, the
PCI interface allows the VLIW core, the DataStreamer DMA controller, and coprocessors to initiate PCI
bus requests. The PCI unit can initiate memory, I/O and configuration commands on the PCI bus.
The BSP-15 DSP can act as a host on the PCI bus. There are three pairs of request/grant lines for other
devices on a PCI bus. This enables a multi-processor configuration to connect up to four BSP-15 DSPs
together on a PCI bus without a bridge. This is very useful for multi-MAP board products.
The PCI interface implements two separate interrupt lines. If the BSP-15 DSP is not the host, any
internal interrupt can be routed to any of these PC interrupts. If the BSP-15 DSP is the host, the PCI
interrupts are sampled by the BSP-15 DSP and can be routed to the BSP-15 DSP ’s VLIW core.
• memory-to-memory: perform block transfers, preload data into the cache, fill a memory region
• memory-to-I/O and I/O-to-memory: perform I/O transfers
• an 8KB internal memory that can be partitioned into as many as 64 variable-sized buffers. Each
• sixty-four independent programmable channels for transfers between various memories and the
• Channel programs, called Descriptor Lists, allow transfers of arbitrary or infinite length to be
• Memories that can be read or written include SDRAM, on-chip memories, and PCI bus accessible
• Interrupts can be triggered by descriptors,
with 0 or 1 bits
buffer is simultaneously the sink for an input I/O or memory channel and the source for an output
I/O or memory channel.
DataStreamer DMA controller’s internal buffer,
specified. Regular and irregular patterns of contiguous or non-contiguous transfers are easy to
specify.
memories. Cache preloading can also be performed.
to be generated.
HWR.BSP15.DS.REV.H
allowing end-of-transfer or mid-stream interrupts
September 6, 2002