BSP-15 Equator Technologies, BSP-15 Datasheet - Page 20

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

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2.1.2.1 Global Registers
2.1.2.2 Breakpoint Registers
2.1.2.3 General Registers
2.1.2.4 Predicate Registers
2.1.2.5 PLC/PLV 128-bit registers
2.2 Interrupts and Exceptions
BSP-15 Processor Datasheet
Global registers on the BSP-15 DSP consist of system registers and implementation-dependent I/O
registers (PIO registers). Dedicated operations manipulate the system registers; conventional load and
store operations manipulate the I/O registers.
BSP-15 DSP has two sets of breakpoint registers: instruction-breakpoint and data-breakpoint registers.
These
Instruction-breakpoint registers cause an exception when an operation in the specified address is about
to be executed. Similarly, the data-breakpoint registers cause an exception when the data at the specified
address is about to be accessed. In both cases, a mask can be used to specify a range of addresses.
By registering an exception handling routine associated with either of these exceptions, a software
developer can control what happens when a hardware breakpoint occurs. For example, the exception
handling routine may be used to signal an external application such as a source-level debugger that a
breakpoint has occurred.
There are 128 32-bit registers that can be treated as 64-bit general registers using even-odd pairs of the
32-bit registers.
There are 32 1-bit predicate registers. Predicate registers are used in predicated operations, logical
operations, and branches. They provide a destination for operations with a judged condition.
The IG-ALU has eight special 128-bit registers – two pairs of Partitioned Local Constant (PLC)
registers and two pairs of Partitioned Local Variable (PLV) registers. These registers are used for
powerful SIMD DSP partitioned operations. The registers can be configured as sixteen 8-bit operation
partitions, eight 16-bit operation partitions, or four 32-bit operation partitions. For numerous digital
signal processing and compression algorithms, the SIMD operations allows the BSP-15 DSP to match
the cost/performance of fixed-function chips without the loss of re-programmability.
The BSP-15 DSP has a flexible interrupt structure. Interrupts and exceptions internal to the core are
reflected directly in system registers. All other interrupts from on-chip devices and PCI interrupts from
external devices are gathered by an on-chip interrupt controller. The interrupt controller also provides a
number of software interrupts.
Routing, masking, and prioritization of interrupts is completely software programmable. Each of the
interrupts handled by the interrupt controller can be individually masked, or routed to one of four core
interrupts or to one of two PCI interrupt signals.
registers
provide
hardware
HWR.BSP15.DS.REV.H
breakpoint
capability
for
various
debugging
September 6, 2002
tools.