BSP-15 Equator Technologies, BSP-15 Datasheet - Page 23

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

2.4.1 Caches
2.4.2 Address Translation
2.5 Databuses and Controllers
2.5.1 Memory Interface Controller
September 6, 2002
DataStreamer DMA controller and for external use via PCI. The line buffer memory is used to store the
content of Flash ROM at system boot up.
The BSP-15 DSP has a 32 KB instruction cache and a separate, multi-bank 32 KB data cache. Both
caches are physically addressed, so that problems of aliasing and context switching do not arise. For fast
address translation, the cache index is virtual but the tags are physical.
The instruction cache holds instructions in a compressed form. It is organized as a two-way set
associative cache with a LRU replacement algorithm.
The data cache is a 32 KB, four-way set-associative (with true LRU replacement), write-back cache.
The data cache supports four simultaneous 64-bit data accesses per cycle. The cache is non-blocking; up
to eight outstanding misses to different cache lines and up to 48 outstanding misses overall are allowed.
The BSP-15 DSP provides memory management support in the form of separate TLBs for the
instruction stream, each I-ALU data access, and the DataStreamer DMA controller. The four TLBs
(ITLB, two DTLBs, and DSTLB) can be programmed independently.
The DTS-ID is part of the virtual address and can be used to direct accesses when the TLBs are
disabled.
Each TLB has sixteen fully-associative entries. Each entry contains a Virtual Page Number (VPN), an
8-bit Address Space Identifier (ASID), access protection bits, and page size information. Each entry can
map a page of any valid size, where the valid sizes are 16KB, 64KB, 256KB, 1MB, 4MB, 16MB,
64MB, 256MB, and 1GB.
When a TLB miss occurs, an exception is generated. The exception handler can modify a TLB entry and
retry the failed operation. Separate exception handlers can be installed for data, instruction, and
DataStreamer DMA controller TLB misses.
The various buses and controllers on the BSP-15 DSP are described in the following sections.
The Memory Controller Unit allows customers to easily build high-performance, external memory up to
128MB using SDRAM/SGRAM without any external glue logic. Local memory supports externally
initiated PCI accesses through the Address Translation Unit within the PCI module.
The Memory Controller Unit also includes hardware that queues, prioritizes, and transfers data from
memory to memory or from memory to cache asynchronously to the initiating software.
The on-chip core PLL generates the clock for the memory controller and provides clock synchronization
between the BSP-15 DSP and external SDRAM. This provides support for various combinations of
CPU core and memory speeds.
HWR.BSP15.DS.REV.H
BSP-15 Processor Datasheet
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