BSP-15 Equator Technologies, BSP-15 Datasheet - Page 67

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

September 6, 2002
Table 6-11 IIS clock ratios
a.
b. MCLK = audioclk_out; MCLK defaults to 27 MHz on power-up (audio PLL bypassed).
c.
d. Bits/Frame = 2*Bits/Channel = SCLK/LRCLK. When MCLK/LRCLK = 384, 24 bits per channel are always
e.
Table 6-12 IIS output timing parameters
F
t
t
slr
sdo
s
LRCLK
(kHz)
Symbol
Figure 6.5 IIS output timing measurement conditions
48(TDB)
LRCLK = iis_in_lr or iis_out_lr.
SCLK = iis_in_bclk or iis_out_bclk.
transmitted, but the number of valid bits is selectable from 16, 18, 20 or 24.
MCLK defaults to 16.933 MHz when audio PLL is enabled.
44.1
32
a
MCLK
(MHz)
Output sample rate
SCLK falling to LRCLK delay
SCLK falling to SDATA valid
16.933
12.288
12.288
Description
iis_out_data
b
e
iis_out_bclk
iis_out_lr
SCLK
(MHz)
1.536
2.116
1.536
c
HWR.BSP15.DS.REV.H
MCLK/
LRCLK
256
384
384
t
slr
MCLK/
SCLK
8
8
8
Min
–10
–10
t
BITS/
FRAME
sdo
32, 44.1, 48
32
48
48
BSP-15 Processor Datasheet
Max
d
10
10
BITS/
CHANNEL
16
24
24
Unit
kHz
ns
ns
55