BSP-15 Equator Technologies, BSP-15 Datasheet - Page 22

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

10
2.3 Timers
2.4 Memory Hierarchy
BSP-15 Processor Datasheet
Table 2-2
Table 2-2 Supported Interrupts
The BSP-15 DSP has two independent programmable interval timers plus a free-running counter. Each
interval timer has a 32-bit counter register and period register. The counter is incremented once per
cycle. When the counter reaches the period value, the counter is reloaded, a bit is set in the system Event
Seen Register (ESR), and a maskable interrupt is asserted. The free-running counter counts up once per
cycle as well. When it overflows to zero, a bit is set in ESR and a maskable interrupt is asserted.
The transport channel interface also has a programmable timer that counts at a rate of 27 MHz and can
be used to generate an interrupt upon rollover.
The BSP-15 DSP supports several on-chip memories and access to external SDRAM and other
memories via the PCI bus. The VLIW core is equipped with a 32 KB instruction cache and 32 KB data
cache used for caching instructions and data from SDRAM. In addition to supporting I-ALU ports, the
data cache supports a port to the DTS (Data Transfer Switch), which makes data in the data cache
available to the DataStreamer DMA controller.
A 4KB instruction memory and a 4 KB data memory are used by the VLx coprocessor. The Video Filter
uses a 6 KB line buffer memory. These memories, totaling 14 KB, are also accessible from the VLIW
core through un-cached load/store operations. In addition, these memories are also available to the
IrqAlwaysOne
IrqIIC
IrqTCI0
IrqDRC
IrqNTSCIn0
IrqNTSCIn1
IrqTCI1
IrqPCIAA
IrqPCIAB
IrqNTSCOut
IrqIEC958
IrqIIS
IrqPCIAPME
IrqDS0
IrqDS1
IrqDSTLB
IrqDSBufOvrFlow
IrqSoftWare
Name
shows the supported interrupts.
debug interrupt, always asserted
IIC
primary TCI
display refresh controller
primary ITU-R BT.601/656 in
secondary ITU-R BT.601/656 in
secondary TCI
PCI interrupt pin A
PCI interrupt pin B
ITU-R BT.601/656 output
IEC958 audio
IIS audio
PCIA power management event
DS DMA controller interrupt 0
DS DMA controller interrupt 1
DS DMA controller TLB miss
DS DMA controller I/O input overflow
Software-controlled interrupts
Interrupt
HWR.BSP15.DS.REV.H
September 6, 2002