BSP-15 Equator Technologies, BSP-15 Datasheet - Page 19

• Manufacturer Part Number: BSP-15
• Description: Broadband Signal Processor
• Manufacturer: Equator Technologies

2.1.1.1 I-ALU
2.1.1.2 IG-ALU
2.1.1.3 Simple Interlocks
2.1.1.4 Extensive Predication
2.1.2 Register Resources
September 6, 2002
Dynamic address translation and virtual memory protection are fully supported. The 1-bit logical values
are also used to support predicated execution, which substantially enhances available parallelism by
allowing partial speculation and eliminating branching.
The I-ALU performs the following operations:
Certain operations require more than one cycle to complete. No hardware interlocks are needed to
prevent issue of an operation that attempts to read a result not yet completed. The VLIW compiler is
responsible for correct scheduling, not hardware. Register scoreboarding is supported for outstanding
loads.
Nearly all operations can have their effect controlled by the value of a selected (1-bit) predicate register.
A predicate register is tested to determine whether or not the operation should be performed. This
allows the compiler to aggressively convert control flow into data flow, enabling a substantially higher
degree of instruction-level parallelism. This also greatly helps to reduce any penalties for branching,
without the cost and complexity of hardware branch prediction typical in other General Purpose
processors.
There are several types of registers on the BSP-15 DSP. These include system registers, breakpoint
registers, general purpose registers, predicate registers, and special purpose 128-bit registers.
The IG-ALU performs the following operations:
• 32-bit integer arithmetic operations including compare
• Logical and bitwise logical operations whose results can be sent to general or predicate registers
• Address calculations for indexed addressing
• Memory reference
• Branching
• System control operations
• 32-bit integer arithmetic operations (same as the I-ALU)
• Logical and bitwise logical operations (same as the I-ALU)
• 64-bit integer arithmetic operations
• Shift/extract/merge operations
• 64-bit SIMD operations (with 8-bit, 16-bit, and 32-bit partitions) including selection, comparison,
• 128-bit partitioned (with 8-bit, 16-bit, and 32-bit partitions) SIMD operations including inner-
selection of maximums and minimums, addition, multiply-add, complex multiplication, inner
product, and sum of absolute differences
product with new partition shift-in for efficient FIR operation and sum of absolute differences
with new partition shift-in for efficient block matching operation
HWR.BSP15.DS.REV.H
BSP-15 Processor Datasheet
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