FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 100

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

12.5.3 Programmed I/O - Transfers from the Host to the FIFO
12.6
Note:
SMSC FDC37C672
If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of (16-
<threshold>) bytes may be read from the FIFO in a single burst.
In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more
bytes free in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty
bit needs to be re-read. Otherwise it may be filled with writeIntrThreshold bytes.
writeIntrThreshold = (16-<threshold>) free bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to
<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in
the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request
by writing data to the FIFO. If at this time the FIFO is empty, it can be completely filled in a single burst,
otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process
is repeated until the last byte is transferred into the FIFO.
Parallel Port Floppy Disk Controller
In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is
selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. These
modes can be selected in the Parallel Port Mode Register, as defined in the Parallel Port Mode Register,
Logical Device 3, at 0xF1. PPFD1 has only drive 1 on the parallel port pins; PPFD2 has drive 0 and 1 on
the parallel port pins.
When the PPFDC is selected the following pins are set as follows:
1.
2.
3.
nPDACK, PDRQ and PINTR refer to the nDACK, DRQ and IRQ chosen for the parallel port.
The following parallel port pins are read as follows by a read of the parallel port register:
1.
2.
3.
The following FDC pins are all in the high impedance state when the PPFDC is actually selected by the
drive select register:
1.
2.
The FDC signals are muxed onto the Parallel Port pins as shown in Table 12.8.
nPDACK: high-Z
PDRQ: not ECP = high-Z, ECP & dmaEn = 0, ECP & not dmaEn = high-Z
PINTR: not active, this is hi-Z or Low depending on settings.
Data Register (read) = last Data Register (write)
Control Register read as "cable not connected" STROBE, AUTOFD and SLC = 0 and nINIT =1
Status Register reads: nBUSY = 0, PE = 0, SLCT = 0, nACK = 1, nERR = 1.
nWDATA, DENSEL, nHDSEL, nWGATE, nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.
If PPFDx is selected, then the parallel port can not be used as a parallel port until "Normal" mode is
selected.
DATASHEET
Page 100
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet