FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 99

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
12.5.1 Programmed I/O Mode or Non-DMA Mode
Note:
12.5.2 Programmed I/O - Transfers from the FIFO to the Host
SMSC FDC37C672
disabling DMA. In order to prevent possible blocking of refresh requests dReq shall not be asserted for
more than 32 DMA cycles in a row. The FIFO is enabled directly by asserting nPDACK and addresses
need not be valid. PINTR is generated when a TC is received. PDRQ must not be asserted for more than
32 DMA cycles in a row.
deasserted for a minimum of 350nsec. (Note: The only way to properly terminate DMA transfers is with a
TC.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting
serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full.
Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1, followed by setting
serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to transfer,
even if the chip continues to request more data from the peripheral.)
The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond
to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO
becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is
required. PDRQ goes inactive after nPDACK goes active for the last byte of a data transfer (or on the
active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ goes inactive due to the
FIFO going empty, then PDRQ is active again as soon as there is one byte in the FIFO. If PDRQ goes
inactive due to the TC, then PDRQ is active again when there is one byte in the FIFO, and serviceIntr has
been re-enabled. (Note: A data underrun may occur if PDRQ is not removed in time to prevent an
unwanted cycle.)
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software
can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test
Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo located
at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first sets up the
direction and state, sets dmaEn to 0 and serviceIntr to 0.
The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed
I/O will empty or fill the FIFO using the appropriate direction and mode.
A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.
In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available
in the FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise
readIntrThreshold bytes may be read from the FIFO in a single burst.
readIntrThreshold = (16-<threshold>) data bytes in FIFO
An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or
equal to (16-<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in
the FIFO.) The PINT pin can be used for interrupt-driven systems. The host must respond to the request
by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO.
After the 32nd cycle, PDRQ must be kept unasserted until nPDACK is
DATASHEET
Page 99
Rev. 10-29-03