FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 73

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
9.4
SMSC FDC37C672
BAUD RATE
Table 9.3 - Baud Rates Using 1.8462 MHz Clock for <= 38.4K; Using 1.8432MHz Clock for 115.2k; Using
DESIRED
134.5
1200
1800
110
150
300
600
50
75
C. When a timeout interrupt has occurred it is cleared and the timer reset when the CPU reads one
D. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received
When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT
interrupts occur as follows:
A.
B.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received
data available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register
empty interrupt.
FIFO Polled Mode Operation
With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or 3 or all to zero puts the UART in the FIFO Polled Mode of
operation. Since the RCVR and XMITTER are controlled separately, either one or both can be in the
polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the
LSR. LSR definitions for the FIFO Polled Mode are as follows:
Bit 0=1 as long as there is one byte in the RCVR FIFO.
Bits 1 to 4 specify which error(s) have occurred. Character error status is handled the same way as when
in the interrupt mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift register are empty.
Bit 7 indicates whether there are any errors in the RCVR FIFO.
There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the
RCVR and XMIT FIFOs are still fully capable of holding characters.
character from the RCVR FIFO.
or after the CPU reads the RCVR FIFO.
The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty; it is cleared as
soon as the transmitter holding register is written to (1 of 16 characters may be written to the XMIT
FIFO while servicing this interrupt) or the IIR is read.
The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time
whenever the following occurs: THRE=1 and there have not been at least two bytes at the same time
in the transmitter FIFO since the last THRE=1. The transmitter interrupt after changing FCR0 will be
immediate, if it is enabled.
GENERATE 16X CLOCK
DIVISOR USED TO
PRELIMINARY DATASHEET
3.6864MHz Clock for 230.4k; Using 7.3728 MHz Clock for 460.8k
2304
1536
1047
857
768
384
192
96
64
PERCENT ERROR DIFFERENCE BETWEEN
Page 73
DESIRED AND ACTUAL
(Note 9.2)
0.001
0.004
-
-
-
-
-
-
-
BIT 7 OR 6
CRXX:
Rev. 10-29-03
X
X
X
X
X
X
X
X
X