FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 127

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
Power Mgmt
Default = 0x00.
on Vcc POR or
Reset_Drv hardware
signal
OSC
Default = 0x04, on Vcc
POR or Reset_Drv
hardware signal.
Chip Level
Vendor Defined
Configuration Address
Byte 0
Default
=0
=0
on Vcc POR or
Reset_Drv
Configuration Address
Byte 1
Default = 0x03
on Vcc POR or
Reset_Drv
Default = 0x00
on VCC POR and
Hard Reset
Chip Level
Vendor Defined
TEST 4
Default = 0x00, on Vcc
POR
x
x
F0 (Sysopt=0)
70 (Sysopt=1)
REGISTER
0x29 -0x2A
ADDRESS
0x23 R/W
0x24 R/W
0x2B R/W
0x25
0x26
0x27
0x28
Bit[0] FDC
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6:7] Reserved (read as 0)
= 0
= 1
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01 Osc is on, BRG clock is on.
= 10 Same as above (01) case.
= 00 Osc is on, BRG Clock Enabled.
= 11 Osc is off, BRG clock is disabled.
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0
= 1
Bit[7] Reserved
Reserved - Writes are ignored, reads return 0.
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 19.4
Bit[7:0] Configuration Address Bits [15:8]
See Note 19.4
Bits[7:0] Reserved - Writes are ignored, reads return 0.
Reserved - Writes are ignored, reads return 0.
Test Modes: Reserved for SMSC. Users should not write
to this register, may produce undesired results.
DATASHEET
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
PLL is on (backward Compatible)
PLL is off
12-Bit Address Qualification
16-Bit Address Qualification
Page 127
DESCRIPTION
Rev. 10-29-03
STATE
C
C
C
C
C