FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 52

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Notes:
8.1.4
SMSC FDC37C672
MT
NC: No Change, the same value as the one at the beginning of command execution.
LSB: Least Significant Bit, the LSB of H is complemented.
0
1
information read from each sector with the specified value in the command and sets the ND flag of Status
Register 1 to a "1" if there is no comparison. Multi-track or skip operations are not allowed with this
command. The MT and SK bits (bits D7 and D5 of the first command byte respectively) should always be
set to "0".
This command terminates when the EOT specified number of sectors has not been read. If the FDC does
not find an ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it
sets the IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to
"1", and terminates the command.
Write Data
After the Write Data command has been issued, the FDC loads the head (if it is in the unloaded state),
waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID
fields. When the sector address read from the diskette matches the sector address specified in the
command, the FDC reads the data from the host via the FIFO and writes it to the sector's data field.
After writing data into the current sector, the FDC computes the CRC value and writes it into the CRC field
at the end of the sector transfer. The Sector Number stored in "R" is incremented by one, and the FDC
continues writing to the next data field. The FDC continues this "Multi-Sector Write Operation". Upon
receipt of a terminal count signal or if a FIFO over/under run occurs while a data field is being written, then
the remainder of the data field is filled with zeros. The FDC reads the ID field of each sector and checks
the CRC bytes. If it detects a CRC error in one of the ID fields, it sets the IC code in Status Register
0 to "01" (abnormal termination), sets the DE bit of Status Register 1 to "1", and terminates the Write Data
command.
The Write Data command operates in much the same manner as the Read Data command. The following
items are the same. Please refer to the Read Data Command for details:
Transfer Capacity
EN (End of Cylinder) bit
ND (No Data) bit
Head Load, Unload Time Interval
ID information when the host terminates the command
Definition of DTL when N = 0 and when N does not = 0
HEAD
0
1
0
1
TRANSFERRED TO
FINAL SECTOR
Less than EOT
Less than EOT
Less than EOT
Less than EOT
Equal to EOT
Equal to EOT
Equal to EOT
Equal to EOT
HOST
Table 8.5 - Result Phase Table
DATASHEET
Page 52
C + 1
C + 1
C + 1
NC
NC
NC
NC
NC
C
ID INFORMATION AT RESULT PHASE
LSB
LSB
NC
NC
NC
NC
NC
NC
H
Enhanced Super I/O Controller with Fast IR
R + 1
R + 1
R + 1
R + 1
01
01
01
01
R
Rev. 10-29-03
NC
NC
NC
NC
NC
NC
NC
NC
N
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