FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 27

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Note:
Note:
SMSC FDC37C672
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 6.10 for the settings corresponding to
the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250
Kbps after a hardware reset.
BIT 2 through 4 PRECOMPENSATION SELECT
These three bits select the value of write precompensation that will be applied to the WDATA output
signal. Table 6.9 shows the precompensation values for the combination of these bits settings. Track 0 is
the default starting track number to start precompensation. this starting track number can be changed by
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy
controller
Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator
circuits will be turned off. The controller will come out of manual low power
*2Mbps data rate is only available if V
clock
PRELIMINARY DATASHEET
and data mode after a software reset or access to the Data Register or Main Status
PRECOMP
Table 6.9 - Precompensation Delays
432
111
001
010
011
100
101
110
000
CC
= 5V.
Default: See Table 6.11
PRECOMPENSATION
Page 27
<2MBPS
Default
125.00
166.67
208.33
250.00
41.67
83.34
0.00
DELAY (NSEC)
2MBPS*
Default
104.2
20.8
41.7
62.5
83.3
125
0
Rev. 10-29-03