FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 142

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

SMSC FDC37C672
WDT_VAL
Default = 0x00
on Vcc POR or
Reset_Drv
WDT_CFG
Default = 0x00
on Vcc POR or
Reset_Drv
WDT_CTRL
Default = 0x00
Cleared by VTR POR
NAME
REG INDEX
0xF2
0xF3
0xF4
Watch-dog Timer Time-out Value
Binary coded, units = minutes(default) or seconds, selectable
0x00 Time out disabled
0x01 Time-out = 1 minute (second)
0xFF Time-out = 255 minutes (seconds)
Watch-dog timer Configuration
Bit[0] Joy-stick Enable
=1
=0
Bit[1] Keyboard Enable
=1
=0
Bit[2] Mouse Enable
=1
=0
Bit[3] Reserved
Bits[7:4] WDT Interrupt Mapping
1111 = IRQ15
0011 = IRQ3
0010 = Invalid
0001 = IRQ1
0000 = Disable
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0
Bit[1] Reserved
Bit[2] Force Timeout, W
=1
Bit[3] P20 Force Timeout Enable, R/W
= 1
= 0
Note: The P20 signal will remain high for a minimum of 1us
Bit[7:4] Reserved. Set to 0
DATASHEET
via Bit[7] of Reg 0xF1, LD 8.
WDT is reset upon an I/O read or write of the Game
Port
WDT is not affected by I/O reads or writes to the Game
Port.
WDT is reset upon a Keyboard interrupt.
WDT is not affected by Keyboard interrupts.
WDT is reset upon a Mouse interrupt
WDT is not affected by Mouse interrupts.
WD timeout occurred
WD timer counting
Forces WD timeout event; this bit is self-clearing
Allows rising edge of P20, from the Keyboard
Controller, to force the WD timeout event. A WD
timeout event may still be forced by setting the Force
Timeout Bit, bit 2.
P20 activity does not generate the WD timeout event.
and can remain high indefinitely. Therefore, when P20
forced timeouts are enabled, a self-clearing edge-
detect circuit is used to generate a signal which is
ORed with the signal generated by the Force Timeout
Bit.
Page 142
DEFINITION
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
STATE
Datasheet
C
C
C