FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 86

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

SMSC FDC37C672
nWRITE
PD<0:7>
INTR
WAIT
DATASTB
RESET
ADDRSTB
PE
SLCT
nERR
PDIR
SIGNAL
EPP
6.
7.
EPP 1.7 Read
The timing for a read operation (data) is shown in timing diagram EPP 1.7 Read Data cycle. IOCHRDY is
driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle
time. The read cycle can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
When the host deasserts nIOW the chip deasserts nDATASTB or nADDRSTRB and latches the data
from the SData bus for the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
The host sets PDIR bit in the control register to a logic "1". This deasserts nWRITE and tri-states the
PData bus.
The host selects an EPP register and drives nIOR active.
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus is tri-stated, PDIR is set and the
nWRITE signal is valid.
If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out
occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination
phase of the cycle.
When the host deasserts nIOR the chip deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
nWrite
Address/Data
Interrupt
nWait
nData Strobe
nReset
nAddress Strobe
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Status
Error
Parallel Port
Direction
EPP NAME
TYPE
I/O
O
O
O
O
O
I
I
I
I
I
Table 12.2 - EPP Pin Descriptions
DATASHEET
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
This signal is active high and positive edge triggered. (Pass through
with no inversion, Same as SPP.)
This signal is active low. It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is ready
for the next transfer.
This signal is active low. It is used to denote data read or write
operation.
This signal is active low. When driven active, the EPP device is reset
to its initial operational mode.
This signal is active low. It is used to denote address read or write
operation.
Same as SPP mode.
Same as SPP mode.
Same as SPP mode.
This output shows the direction of the data transfer on the parallel port
bus. A low means an output/write condition and a high means an
input/read condition. This signal is normally a low (output/write)
unless PCD of the control register is set or if an EPP read cycle is in
progress.
Page 86
EPP DESCRIPTION
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet