FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 128

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Note 19.4 To allow the selection of the configuration address to a user defined location, these Configuration Address
Note:
19.2.6 Logical Device Configuration/Control Registers [0x30-0xFF]
SMSC FDC37C672
TEST 5
Default = 0x00, on Vcc
POR
TEST 1
Default = 0x00, on Vcc
POR
TEST 2
Default = 0x00, on Vcc
POR
TEST 3
Default = 0x00, on Vcc
POR
Activate (Note 19.5)
Default = 0x00
on Vcc POR or Reset_Drv
Logical Device Control
LOGICAL DEVICE
REGISTER
REGISTER
Bytes are used. There is no restriction on the address chosen, except that A0 is 0, that is, the address
must be on an even byte boundary. As soon as both bytes are changed, the configuration space is moved
to the specified location with no delay (Note: Write byte 0, then byte 1; writing CR27 changes the base
address).
The configuration address is only reset to its default address upon a Hard Reset or Vcc POR.
The default configuration address is either 3F0 or 370, as specified by the SYSOPT pin.
This change affects SMSC Mode only.
Used to access the registers that are assigned to each logical unit. This chip supports nine logical units
and has nine sets of logical device registers. The six logical devices are Floppy, Parallel, Serial 1, Serial
2, Keyboard Controller, and Auxiliary_I/O. A separate set (bank) of control and configuration registers
exists for each logical device and is selected with the Logical Device # Register (0x07).
The INDEX PORT is used to select a specific logical device register. These registers are then accessed
through the DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration State. The logical
register addresses are shown in the table below.
ADDRESS
0x2C R/W
0x2D R/W
0x2E R/W
0x2F R/W
(0x31-0x37)
ADDRESS
(0x30)
Table 19.3 - Logical Device Registers
Test Modes: Reserved for SMSC. Users should not write
to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not write
to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not write
to this register, may produce undesired results.
Test Modes: Reserved for SMSC. Users should not write
to this register, may produce undesired results.
DATASHEET
Bits[7:1] Reserved, set to zero.
Bit[0]
= 1
= 0
Reserved - Writes are ignored, reads return 0.
Page 128
Activates the logical device currently selected
through the Logical Device # register.
Logical device currently selected is inactive
DESCRIPTION
DESCRIPTION
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
STATE
STATE
Datasheet
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