FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 89

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
nStrobe
PData 7:0
nAck
PeriphAck (Busy)
PError
(nAckReverse)
Select
nAutoFd
(HostAck)
nFault
(nPeriphRequest)
nInit
nSelectIn
NAME
TYPE
I/O
O
O
O
O
I
I
I
I
I
During write operations nStrobe registers data or address into the slave on the
asserting edge (handshakes with Busy).
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal
handshakes with nAutoFd in reverse.
This signal deasserts to indicate that the peripheral can accept data. This signal
handshakes with nStrobe in the forward direction. In the reverse direction this
signal indicates whether the data lines contain ECP command information or data.
The peripheral uses this signal to flow control in the forward direction. It is an
"interlocked" handshake with nStrobe. PeriphAck also provides command
information in the reverse direction.
Used to acknowledge a change in the direction the transfer (asserted = forward).
The peripheral drives this signal low to acknowledge nReverseRequest. It is an
"interlocked" handshake with nReverseRequest. The host relies upon
nAckReverse to determine when it is permitted to drive the data bus.
Indicates printer on line.
Requests a byte of data from the peripheral when asserted, handshaking with
nAck in the reverse direction. In the forward direction this signal indicates whether
the data lines contain ECP address or data. The host drives this signal to flow
control in the reverse direction. It is an "interlocked" handshake with nAck. HostAck
also provides command information in the forward phase.
Generates an error interrupt when asserted. This signal provides a mechanism for
peer-to-peer communication. This signal is valid only in the forward direction.
During ECP Mode the peripheral is permitted (but not required) to drive this pin low
to request a reverse transfer. The request is merely a "hint" to the host; the host
has ultimate control over the transfer direction. This signal would be typically used
to generate an interrupt to the host CPU.
Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is
driven low to place the channel in the reverse direction. The peripheral is only
allowed to drive the bi-directional data bus while in ECP Mode and HostAck is low
and nSelectIn is high.
Always deasserted in ECP mode.
Table 12.3 - ECP Pin Descriptions
DATASHEET
Page 89
DESCRIPTION
Rev. 10-29-03