FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 76

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Note 9.3 DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 9.4 Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 9.5 When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Note 9.6 This bit no longer has a pin associated with it.
Note 9.7 When operating in the XT mode, this register is not available.
Note 9.8 These bits are always zero in the non-FIFO mode.
Note 9.9 Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 9.10 The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime
9.5
9.5.1
SMSC FDC37C672
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
Notes on Serial Port Operation
FIFO Mode Operation:
GENERAL
The RCVR FIFO will hold up to 16 bytes regardless of which trigger level is selected.
TX AND RX FIFO OPERATION
The Tx portion of the UART transmits data through TXD as soon as the CPU loads a byte into the Tx
FIFO. The UART will prevent loads to the Tx FIFO if it currently holds 16 characters. Loading to the
Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These
capabilities account for the largely autonomous operation of the Tx.
The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt
whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume
that the Tx FIFO is empty and the CPU starts to load it. When the first byte enters the FIFO the Tx FIFO
empty interrupt will transition from active to inactive. Depending on the execution speed of the service
routine software, the UART may be able to transfer this byte from the FIFO to the shift register before the
CPU loads another byte. If this happens, the Tx FIFO will be empty again and typically the UART's
interrupt line would transition to the active state. This could cause a system with an interrupt control unit to
record a Tx FIFO empty condition, even though the CPU is currently servicing that interrupt. Therefore,
after the first byte has been loaded into the FIFO the UART will wait one serial character
transmission time before issuing a new Tx FIFO empty interrupt. This one character Tx interrupt
delay will remain active until at least two bytes have been loaded into the FIFO, concurrently.
When the Tx FIFO empties after this condition, the Tx interrupt will be activated without a one
character delay.
Rx support functions and operation are quite different from those described for the transmitter. The Rx
FIFO receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that
time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue
to store bytes until it holds 16 of them. It will not accept any more data when it is full. Any more data
entering the Rx shift register will set the Overrun Error flag. Normally, the FIFO depth and the
programmable trigger levels will give the CPU ample time to empty the Rx FIFO before an overrun occurs.
DATASHEET
Page 76
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet