FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 93

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
SMSC FDC37C672
The tFIFO will not stall when overwritten or underrun. If an attempt is made to write data to a full tFIFO,
the new data is not accepted into the tFIFO. If an attempt is made to read data from an empty tFIFO, the
last data byte is re-read again. The full and empty bits must always keep track of the correct FIFO state.
The tFIFO will transfer data at the maximum ISA rate so that software may generate performance metrics.
The FIFO size and interrupt threshold can be determined by writing bytes to the FIFO and checking the full
and serviceIntr bits.
The writeIntrThreshold can be determined by starting with a full tFIFO, setting the direction bit to 0 and
emptying it a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate
that the threshold has been reached.
The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at
a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has
been reached.
Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if
44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the same order as
was written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read, 10H is returned. This indicates to the system that this is
an 8-bit implementation. (PWord = 1 byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low level. This means that this chip does not support hardware
RLE compression. It does support hardware de-compression!
BIT 6 intrValue
Returns the value on the ISA iRq line to determine possible conflicts.
BITS [3:0] Parallel Port IRQ
Refer to Table 12.6B.
BITS [2:0] Parallel Port DMA
Refer to Table 12.6C.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
DATASHEET
Page 93
Rev. 10-29-03