dp8344b National Semiconductor Corporation, dp8344b Datasheet

dp8344b

Manufacturer Part Number

dp8344b

Description

Biphase Communications Processor?bcp

Manufacturer

National Semiconductor Corporation

Datasheet

1.DP8344B.pdf (184 pages)

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C 1995 National Semiconductor Corporation

DP8344B Biphase Communications Processor BCP

General Description

The DP8344B BCP is a communications processor de-

signed to efficiently process IBM

communications protocols A general purpose 8-bit protocol

is also supported

The BCP integrates a 20 MHz 8-bit Harvard architecture

RISC processor and an intelligent software-configurable

transceiver on the same low power microCMOS chip The

transceiver is capable of operating without significant proc-

essor interaction releasing processor power for other tasks

Fast and flexible interrupt and subroutine capabilities with

on-chip stacks make this power readily available

The transceiver is mapped into the processor’s register

space communicating with the processor via an asynchro-

nous interface which enables both sections of the chip to

run from different clock sources The transmitter and receiv-

er run at the same basic clock frequency although the re-

ceiver extracts a clock from the incoming data stream to

ensure timing accuracy

The BCP is designed to stand alone and is capable of imple-

menting a complete communications interface using the

processor’s spare power to control the complete system

Alternatively the BCP can be interfaced to another proces-

sor with an on-chip interface controller arbitrating access to

data memory Access to program memory is also possible

providing the ability to download BCP code

A simple line interface connects the BCP to the communica-

tions line The receiver includes an on-chip analog compar-

ator suitable for use in a transformer-coupled environment

Block Diagram

BCP and TRI-STATE are registered trademarks of National Semiconductor Corporation

IBM is a registered trademark of International Business Machines Corporation

TL F 9336

3270 3299 and 5250

Typical BCP System

FIGURE 1

although a TTL-level serial input is also provided for applica-

tions where an external comparator is preferred

A typical system is shown below Both coax and twinax line

interfaces are shown as well as an example of the (option-

al) remote processor interface

Features

Transceiver

Processor

General

Software configurable for 3270 3299 5250 and general

8-bit protocols

Fully registered status and control

On-chip analog line receiver

20 MHz clock (50 ns T-states)

Max instruction cycle 200 ns

33 instruction types (50 total opcodes)

ALU and barrel shifter

64k x 8 data memory address range

64k x 16 program memory address range

(note typical system requires

Programmable wait states

Soft-loadable program memory

Interrupt and subroutine capability

Stand alone or host operation

Flexible bus interface with on-chip arbitration logic

Low power microCMOS typ I

84-pin plastic leaded chip carrier (PLCC) package

2k program memory)

25 mA at 20 MHz

RRD-B30M105 Printed in U S A

November 1991

TL F 9336 – 51

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