dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 27

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

2 0 CPU Description
In addition to the above jump call and return program flow
instructions the BCP is capable of generating software in-
terrupts via the TRAP instruction This instruction generates
a call to any one of 64 possible interrupt table addresses
based on its vector number operand This allows both the
simulation of hardware interrupts and the construction of
special software interrupts if desired The actual interrupt
table entry address is determined by concatenating the In-
terrupt Base Register
the vector number operand in the TRAP instruction This
instruction may also clear the GIE bit if desired Table
2-20 shows the syntax and operation of the TRAP instruc-
tion
Note PC
TRAP v
IBR
Optional operands may either be specified or omitted
Syntax
GIE
e
e
e
e
concatenation operator combines operands together forming one long operand
e
surrounds optional operands that are not part of the instruction syntax
Program Counter contents initially points to instruction following call
Interrupt Base Register
Global Interrupt Enable bit
IBR
g
to an 8-bit representation of
PC
If ‘‘g ’’
Form PC address as shown below
Note GIE
reg Bank Selection
(Continued)
EXX ba bb
GIE
e
Optional operands may either be specified or omitted
Syntax
1 then clear GIE
e
e
surrounds optional operands that are not part of the instruction syntax
ALU flags
Global Interrupt Enable bit
TABLE 2-20 TRAP Instruction
TABLE 2-21 EXX Instruction
g
Instruction Operation
x
Case ‘‘ba’’ of
End case
Case ‘‘bb’’ of
End case
Case ‘‘g’’ of
End case
0 activate Main Bank A
1 activate Alternate Bank A
0 activate Main Bank B
1 activate Alternate Bank B
0 leave GIE unaffected (default)
1 (reserved)
2 set GIE
3 clear GIE
Address Stack
Instruction Operation
27
Miscellaneous Instructions
As stated in the ‘‘CPU Register Set’’ section the BCP has
44 registers with 24 of them arranged into four register
banks Main Bank A Alternate Bank A Main Bank B and
Alternate Bank B The exchange instruction EXX selects
which register banks are currently available to the CPU for
example either Main Bank A or Alternate Bank A The dese-
lected register banks retain their current values The EXX
instruction can also alter the state of GIE if desired Table
2-21 shows the EXX instruction syntax and operation
Operand Range
0 63