dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 74

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4 0 Remote Interface and Arbitration System (RIAS)
The last possible Memory Selection is Instruction Memory
access depend on if RASM is expecting the low byte or high
byte Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB)
If HIB is low the next state is RS
byte is MUXed to the AD bus If HIB is high the high instruc-
tion byte is MUXed to AD and RS
access like a DMEM access is subject to wait states and
these states will be looped on until all programmed instruc-
tion memory wait states have been inserted
Note Resetting the BCP will reset HIB (i e HIB
After all of the programmed wait states are inserted in the
RS
WAIT low a half T-state before the end of the last pro-
grammed wait state If there are no programmed wait
states WAIT must be asserted low a half T-state before the
end of RS
remote access is extended indefinitely All the RS
move to their corresponding RS
after the programmed wait state conditions are met and
WAIT is high The RS
REM-RD is deasserted LCL remains high in all RS
and A remains in TRI-STATE AD will also stay in TRI-
STATE if the access was to DMEM XACK is taken back
high to indicate that data is now valid on the read If XACK is
connected to a Remote Processor wait pin it is no longer
waited and can now terminate its read cycle This state be-
gins the Termination Phase The action specified in the con-
ditional box is only executed while RAE REM-RD is assert-
ed a clock edge is not necessary In all RS
RS
RAE REM-RD is deasserted In RS
through the whole state
On the CPU-CLK after RAE REM-RD is deasserted RASM
enters RS
RS
CPU-CLK is high (i e for the first half T-state of RS
MS1 – 0
D
E4
F1
states more wait states may be added by asserting
Memory Select bits in RIC (i e
will also force HIB to zero This way the instruction word boundary
can be reset without resetting the BCP
LCL remains low and A remains in TRI-STATE while
(DMEM) LCL will fall a propagation delay after
e
F1
D
01 The two possible next states for an IMEM
from every RS
to add wait states If WAIT remains low the
E
states are looped upon until RAE
E
state except RS
E
MS1–0
D5
D6
states on the CPU-CLK
and the low instruction
E4
is entered An IMEM
e
e
LCL remains high
01 pointing to IMEM)
0) Writing 01 to the
E
E4
states except
(DMEM) In
D
E
F1
states
states
)
74
From RS
RAE REM-RD is deasserted In RS
while both A and AD remain in TRI-STATE
From RS
back to state RS
Access is initiated If the access was to IMEM then the last
action of the remote access before returning to RS
switch HIB and increment the PC if the high byte was read
From RS
LCL returns low but A and AD remain TRI-STATE for the
first half T-state of RS
the next state will be RS
Remote Access is initiated
The example in Figure 4-15 shows the BCP executing the
first of two consecutive Data Memory reads when REM-RD
goes low In response XACK goes low waiting the remote
processor At the end of the first instruction although the
BCP begins its second read by taking ALE high the RASM
now takes control of the bus and takes LCL high at the end
of T
that READ has been deasserted before the data bus is
switched The Timing Control Unit is now waited inserting
remote access wait states T
The remote address is permitted one T-state to settle on the
BCP address bus before READ goes low XACK then re-
turns high one T-state plus the programmed Data Memory
wait state T
time The Remote Processor will respond by deasserting
REM-RD high to which the BCP in turn responds by deas-
serting READ high Following READ being deasserted high
the BCP waits till the end of the next T-state before taking
LCL low again ensuring that the read cycle has concluded
before the bus is switched Control is then returned to the
Timing Control Unit and the local memory read continues
4 2 2 Latched Read
This mode differs from the Buffered Read mode in the way
the access is terminated A latched Read cycle ends after
the data being read is valid and the termination doesn’t wait
for the trailing edge of REM-RD Therefore the Arbitration
and Access Phases of the Latched Read mode are the
same as for the Buffered Read mode The complete flow
chart for the Latched Read mode is shown in Figure 4-16
1
A one T-state delay is built into this transfer to ensure
F2
F1
E4
the next CPU-CLK returns to state RS
Wd
the next clock will return the state machine
RASM enters RS
later having satisfied the memory access
A1
(Continued)
where it will loop until another Remote
A3
A1
If no Remote Access is initiated
where it will loop until another
Wr
F2
as RASM takes over
on the CPU-CLK after
F2
LCL remains high
A3
A
where
is to