dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 21

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

2 0 CPU Description
Indexed Addressing Modes
Indexed operands involve one of four possible CPU register
pairs referred to as the index registers Figure 2-4 illustrates
how the index registers map into the CPU Register Set
Note that the index registers are 16 bits wide
Index registers allow for indirect memory addressing and
usually contain data memory addresses although the
LJMP instruction can use index registers to hold instruction
memory addresses Most of the instructions that allow
memory indirect addressing (i e the use of index registers)
also allow pre-incrementing post-incrementing or post-dec-
rementing of the index register contents during instruction
execution if desired Table 2-3 lists the notations used for
the index register modes
The index registers are set to zero when the BCP’s RESET
pin is asserted
Register (MSB)
Index
IW
IY
IX
IZ
15
15
15
15
Note
Note
MOVE Rs Rd
MOVE Rs mIr
MOVE mIr Rd
MOVE Rs Ir
MOVE Ir
MOVE rs IZ
MOVE IZ
MOVE n rd
MOVE n Ir
CPU Register Pair Forming Index Register
FIGURE 2-4 Index Register Map
Notation
IZ
Ir
Syntax
Notation
a
Ir
Ir
Ir
mIr
denotes indirect memory addressing and is part of the instruction syntax
denotes indirect memory addressing and is part of the instruction syntax
a
a
R13
R15
R17
R19
b
a
Ir
A
a
n
a
A Rd
n rd
a
a
n
A
8 7
8 7
8 7
8 7
IZ
Index Register
(Continued)
TABLE 2-3 Index Register Addressing Mode Notations
TABLE 2-4 Relative Index Register Mode Notations
register
register
data memory
register
data memory
register
data memory
instruction memory
instruction memory
a
Type of Action Performed to Calculate a Data Memory Address
Immediate Number (unsigned)
Index Register Contents Not Changed
Index Register Contents Post-Decremented
Index Register Contents Post-Incremented
Index Register Contents Pre-Incremented
General Notation Indicating that Any of the Above Modes Is Allowed
TABLE 2-5 Data Movement Instructions
Instruction Operation
x
x
x
x
R12
R14
R16
R18
register
data memory
data memory
data memory
a
x
x
x
Current Accumulator (unsigned)
(LSB)
register
register
register
x
x
0
0
0
0
register
data memory
21
Immediate-Relative and Register-Relative
Address Modes
The Immediate-Relative mode adds an unsigned 8-bit im-
mediate number to the index register IZ forming a data byte
address The Register-Relative mode adds the unsigned
8-bit value in the current accumulator A to any one of the
index registers forming a data byte address Both of these
indirect memory addressing modes are available only on the
MOVE instruction Table 2-4 shows the notation used for
these two addressing modes
2 1 3 3 Instruction Set Overview
The BCP’s RISC instruction set contains seven categories
of instructions Data Movement Integer Arithmetic Logic
Shift-Rotate Comparison Program Flow and Miscellane-
ous
Data Movement Instructions
The MOVE instruction is responsible for all the data transfer
operations that the BCP can perform Moving one byte at a
time five different types of transfer are allowed register to
register data memory to register register to data memory
instruction memory to register and instruction memory to
data memory Table 2-5 lists all the variations of the MOVE
instruction
x
Meaning
Data Memory Address
Register Register
Register Indexed
Indexed Register
Register Register-Relative
Register-Relative Register
Limited Register Immediate-Relative
Immediate-Relative Limited Register
Immediate Limited Register
Immediate Indexed
x
Addressing Modes
Data Memory Address