dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 137
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dp8344b
Manufacturer Part Number
dp8344b
Description
Biphase Communications Processor?bcp
Manufacturer
National Semiconductor Corporation
Datasheet
1.DP8344B.pdf
(184 pages)
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Figure 6-1
6 0 Reference Section
ADD Add Immediate
Syntax
ADD n rsd
Affected Flags
N Z C V
Description
Adds the immediate value n to the register rsd and places
the result back into the register rsd Note that only the ac-
tive registers R0 – R15 may be specified for rsd The value of
n is limited to 8 bits (unsigned range 0 to 255 signed
range
Example
Add the constant
Instruction Format
T-States
2
Bus Timing
Operation
rsd
ADDA Add with Accumulator
Syntax
ADDA Rs Rd
ADDA Rs mIr
Affected Flags
N Z C V
Description
Adds the source register Rs to the active accumulator and
places the result into the destination specified The destina-
tion may be either a register Rd or data memory via an
index register mode mIr Note that register bank selection
determines which accumulator is active
Example
In the first example the value 4 is placed into the currently
active accumulator that accumulator is added to the con-
tents of register 20 and then the result is placed into regis-
ter 21
In the second example the alternate accumulator of regis-
ter bank B is selected and then added to register 20 The
result is placed into the data memory pointed to by the index
register IZ and then the value of IZ is incremented by one
0
15
ADD
MOVE 4 A
ADDA
EXX
ADDA
Opcode
a
0
n
a
x
0
127 to
R20 R21
0 1
R20 IZ
b
0
rsd
3 R10
11
b
b
128)
a
3 to register 10
immediate limited register
register register
register indexed
and increment data pointer
Place constant into accum
R20
Select alt accumulator
R20
a
a
R10
n
accum
accum
a
(Continued)
(
b
x
x
3)
x
R21
data mem
3
R10
rsd
0
137
Figure 6-1
Instruction Format
ADDA Rs Rd
T-states
ADDA Rs Rd
ADDA Rs mIr
Bus Timing
ADDA Rs Rd
ADDA Rs mIr
Operation
ADDA Rs Rd
Rs
ADDA Rs mIr
Rs
AND And Immediate
Syntax
AND n rsd
Affected Flags
N Z
Description
Logically ANDs the immediate value n to the register rsd
and places the result back into the register rsd Note that
only the active registers R0 – R15 may be specified for rsd
The value of n is 8 bits wide
Example
Unmask both the Transmitter and Receiver interrupts via
the Interrupt Control Register ICR
interrupts unaffected
Instruction Format
T-states
2
Bus Timing
Operation
rsd AND n
ADDA Rs mIr
1
15
0
15
EXX 0 0
AND 11111100B R2
Opcode
a
a
1
1
accumulator
accumulator
Opcode
0
1
0
0
x
11
0
rsd
x
x
0
Rd
data memory
9
immediate limited register
Figure 6-1
Figure 6-6
2
3
select main register banks
unmask transmitter and
receiver interrupts
n
Rd
R2 Leave the other
4
3
Rs
TL F 9336 – 6
rsd
0
0
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