dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 75

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

4 0 Remote Interface and Arbitration System (RIAS)
Until a Remote Read is initiated (RAE REM-RD true) the
state machine (RASM) loops in state RS
Read is initiated and LOR is set high RASM will move to
state RS
buses have been granted locally (i e Local Bus Grant
RASM will move to state RS
in state RS
granted locally If the BCP CPU needs to access Data Mem-
ory while in either RS
do so A local access is requested by the Timing Control
Unit asserting the Local Bus Request (LCL-BREQ) signal A
local bus grant will be given by RASM if the buses are not
being used (as is the case in RS
XACK is taken low as soon as RAE REM-RD is true re-
gardless of an ongoing local access If LOR is low RASM
will move into RS
asserted and there is no local bus request No further local
bus requests will be granted until RASM enters the Termina-
tion Phase If the BCP CPU initiates a Data Memory access
after RS
BCP CPU will remain in state T
reaches the Termination Phase Half a T-state after entering
RS
goes into TRI-STATE
On the next clock RASM enters RS
while XACK remains low The wait state counters i
i
respectively in DCR
to Data Memory) now remains TRI-STATE and the Access
Phase begins
The state machine can move into one of several states
depending on the state of CMD and MS1 – 0 on the next
clock XACK remains low and LCL remains high in all the
possible next states If CMD is high the access is to RIC
and the next state will be RS
AD is RIC
next states all have CMD low and depend on the Memory
Select bits If MS1 – 0 is 10 or 11 the state machine will
enter either RS
Program Counter respectively will be read
DW
B
the A bus (and AD bus if the access is to Data Memory)
are loaded in this state from IW1 – 0 and DW2 – 0
A2
A
A2
the Timing Control Unit will be waited and the
Likewise if a Remote Read is initiated while the
it will not transition in this state The five other
as long as LOR is set high or the buses are
D2
B
or RS
on the next clock after RAE REM-RD is
A
state (and LOCK is high) it can still
The A bus (and AD if the access is
D3
and the low or high bytes of the
A2
D1
The state machine will loop
Wr
A
Since the default state of
)
until the remote access
C
and LCL is taken high
A1
If a Remote
IW
e
and
1)
75
moves RASM into RS
state and A and AD continue to be tri-stated This allows the
Remote Processor to drive the Data Memory address for
the read Since DMEM is subject to wait states RS
looped upon until all the wait states have been inserted
The last possible Memory Selection is Instruction Memory
access depend on if RASM is expecting the low byte or high
byte Instruction words are accessed low byte then high
byte and RASM powers up expecting the low Instruction
byte The internal flag that keeps track of the next expected
Instruction byte is called the High Instruction Byte flag (HIB)
If HIB is low the next state is RS
byte is MUXed to the AD bus If HIB is high the high instruc-
tion byte is MUXed to AD and RS
access like a DMEM access is subject to wait states and
these states will be looped on until all programmed instruc-
tion memory wait states have been inserted
Note Resetting the BCP will reset HIB (i e HIB
After all of the programmed wait states are inserted in the
RS
WAIT low a half T-state before the end of the last pro-
grammed wait state If there are no programmed wait states
WAIT must be asserted low a half T-state before the end of
RS
access is extended indefinitely All the RS
their corresponding RS
programmed wait state conditions are met and WAIT is
high LCL remains high in all RS
TRI-STATE (and AD if the access is to Data Memory)
XACK returns high in this state indicating that data is valid
so that it can be externally latched The action specific to
each RS
RS
This half T-state of hold time is provided to guarantee data
is latched when XACK goes high This state begins the Ter-
mination Phase
MS1 – 0
MS1 – 0
D
D
E
cycle (i e READ is asserted in the first half of RS
to add wait states If WAIT remains low the remote
Memory Select bits in RIC (i e
will also force HIB to zero This way the instruction word boundary
can be reset without resetting the BCP
states more wait states may be added by asserting
D
e
e
state remains in effect during the first half of the
01 The two possible next states for the IMEM
00 designates a Data Memory access and
(Continued)
D4
E
READ will be asserted low in this
states on the CPU-CLK after the
MS1–0
E
D5
D6
states and A remains in
and the low instruction
is entered An IMEM
e
e
D
01 pointing to IMEM)
0) Writing 01 to the
states move to
D4
E4
is
)