dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 163

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

6 0 Reference Section
6 2 REGISTER SET REFERENCE
The register set reference contains detailed information on the bit definitions of all special function registers that are address-
able in the CPU This reference section presents the information in three forms a bit index a register description and bit
definition tables The bit index is an alphabetical listing of all status control bits in the CPU-addressable function registers with a
brief summary of the function The register description is a list of all CPU-addressable special function registers in alphabetical
order The bit definition tables describe the location and function of all control and status bits in the various CPU-addressable
special function registers These tables are arranged by function
6 2 1 Bit Index
An alphabetical listing of all status control bits in the CPU-addressable special function registers with a brief summary of
function Detailed definitions are provided in Section 6 2 3 Bit Definition Tables
4TR
ACK
ASP3 – 0
AT7 – 0
ATA
BIC
BIRQ
C
CCS
COD
DAV
DEME
DS7 – 0
DSP3 – 0
DW2 – 0
FB7 – 0
GIE
IES
IM4 – 0
IV15 – 8
IW1 0
LA
LMBT
LOR
LOOP
LTA
N
OVF
OWP
PAR
POLL
PS2 – 0
RA
RAR
RDIS
RE
RF10 – 8
RFF
RIN
RIS1 0
RLQ
RPEN
RR
RTF7 – 0
RW
SEC
SLR
TA
TCS1 0
TF10 – 8
Bit
Four T-State Read
poll ACKnowledge
Address Stack Pointer
Auxilliary Transceiver control
Advance Transmitter Active
Bi-directional Interrupt Control
Bi-directional Interrupt ReQuest
Carry
CPU Clock Select
Clock Out Disable
Data AVailable
Data Error or Message End
Data Stack
Data Stack Pointer
Data memory Wait-state select
Fill Bits
Global Interrupt Enable
Invalid Ending Sequence
Interrupt Mask select
Interrupt Vector
Instruction memory Wait-state select
Line Active
Loss of Mid Bit Transition
Lock Out Remote
internal LOOP-back
Line Turn Around
Negative
receiver OVerFlow
Odd Word Parity
PARity error
POLL
Protocol Select
Receiver Active
Received Auto-Response
Receiver DISabled while active
Receiver Error
Receive FIFO
Receive FIFO Full
Receiver INvert
Receiver Interrupt Select
Receive Line Quiesce
RePeat ENable
Remote Read
Receive Transmit FIFO
Remote Write
Select Error Codes
Select Line Receiver
Transmitter Active
Transceiver Clock Select
Transmit FIFO
(Continued)
Name
163
ACR
NCF
ISP
ATR
TCR
ACR
CCR
CCR
DCR
ACR
TSR
NCF
DS
ISP
DCR
FBR
ACR
ECR
ICR
IBR
DCR
NCF
ECR
ACR
TMR
NCF
CCR
ECR
TCR
ECR
NCF
TMR
TSR
NCF
ECR
TSR
TSR
NCF
TMR
ICR
TCR
TMR
CCR
RTR
CCR
TCR
TCR
TSR
DCR
TCR
Location
3
1
7 – 4
7 – 0
4
4
4
1
7
2
3
3
7 – 0
3 – 0
2 – 0
7 – 0
0
2
4 – 0
7 – 0
4 3
5
1
1
6
4
3
4
3
3
0
2 – 0
4
2
0
5
2 – 0
6
4
7 6
7
5
6
7 – 0
5
6
5
6
6 5
2 – 0
Timing Control
Receiver Status
Stacks
Receiver Control
Transmitter Control
Interrupt Control
Interrupt Control
Arithmetic Flag
Timing Control
Timing Control
Receiver Status
Receiver Status
Stacks
Stacks
Timing Control
Transmitter Control
Interrupt Control
Receiver Error Code
Interrupt Control
Interrupt Control
Timing Control
Receiver Status
Receiver Error Code
Remote Interface
Transceiver Control
Receiver Status
Arithmetic Flag
Receiver Error Code
Transmitter Control
Receiver Error Code
Receiver Status
Transceiver Control
Receiver Status
Receiver Status
Receiver Error Code
Receiver Status
Receiver Control
Receiver Status
Receiver Control
Interrupt Control
Receiver Control
Receiver Control
Remote Interface
Transceiver Control
Remote Interface
Receiver Control
Receiver Control
Transmitter Status
Transceiver Control
Transmitter Control
Function