dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 12

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

Figures 1-6b and 1-6c show the data path for data memory
1-6f a portion of the Instruction bus is routed through the
1 0 Communications Processor Introduction
ALU MUX and then placed on the destination bus This
data is then stored into the appropriate destination register
accesses For a WRITE operation the source register con-
tents follow the same path through the ALU MUX but the
Destination bus is routed to output pins and on to data
memory For a READ operation incoming data is routed
onto the Destination bus by the ALU MUX and then stored
in a register The address for all data memory accesses is
provided by one of four 16-bit index registers which can
operate in a variety of automatic increment and decrement
modes
Transfer of the data byte between the CPU and the Trans-
ceiver is accomplished through a register location This reg-
ister
to it automatically transfers data to the transmitter FIFO
and reading from it retrieves data from the receiver FIFO
These paths are illustrated in Figures 1-6d and 1-6e
It is also possible to load immediate data into a CPU regis-
ter This data is supplied by the program and is usually a
constant such as a pointer or character As shown in Figure
ALU MUX for this purpose
RTR
appears as a normal CPU register but writing
FIGURE 1-7 Basic Remote Interface
12
Figure 1-7 shows a simplified remote processor interface
1 5 REMOTE INTERFACE AND ARBITRATION SYSTEM
INTRODUCTION
The BCP is designed to serve as a complete stand alone
communications interface Alternately it can be interfaced
with another processor by means of the Remote Interface
and Arbitration System Communication between the BCP
and the remote processor is possible by sharing data mem-
ory Harvard architecture allows the remote system to ac-
cess any BCP data memory location while the BCP contin-
ues to fetch and execute instructions thereby minimizing
performance degradation
This includes tri-state buffers on the address and data bus-
es of the BCP’s Data Memory and all of the control and
handshaking signals required to communicate between the
BCP and the host system
There is an 8-bit control register Remote Interface Control
to control a variety of features including the types of memo-
ry accesses interface speeds single step program execu-
tion CPU start stop instruction memory loads and so forth
Detailed information on all interface options is provided in
the section on Remote Interface and Arbitration System
and in the related Reference section
RIC
accessible only to the remote system which is used
(Continued)
TL F 9336 – C9