dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 65

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

Figure 4-6 The access is initiated by asserting RAE and
Figure 4-7(c) shows the data path from the Program Coun-
4 0 Remote Interface and Arbitration System (RIAS)
Remote Accesses other than to RIC are accomplished
with the CMD pin low in conjunction with asserting RAE low
along with REM-WR or REM-RD being taken low The type
of access performed is defined by the Memory Select bits in
Reads or writes of Data Memory (DMEM) are preceded by
setting the Memory Select bits in RIC for a DMEM ac-
cess
writes to BCP Data Memory as many times as it needs to A
DMEM access as well as a RIC access can be made
while the BCP CPU is executing instructions All other ac-
cesses must be executed with the BCP CPU stopped
The timing for a Data Memory read and write are shown in
REM-RD or REM-WR while CMD is low The BCP responds
by bringing its address and data lines into TRI-STATE and
allowing the RP to control DMEM READ is asserted in the
Access Phase of a Remote Read Figure 4-6(a) It will stay
low for a minimum of one T-state but can be extended by
adding programmable data wait states or by taking WAIT
low WRITE is asserted in the Access Phase with a remote
write It too is a minimum of one T-state and can be in-
creased by adding programmable wait states or by taking
WAIT low
ter to the AD bus Both high and low PC bytes can be writ-
ten or read through AD The RP has independent control of
the high and low bytes of the Program Counter the byte
being accessed is specified in the Memory Select bits The
high byte of the PC is accessed by setting MS1 – 0
Setting MS1 – 0
PC After the Memory Select bits are set by a Remote Write
to RIC the byte selected can be read or written by the RP
by executing a Remote Access with CMD low Remote ac-
cesses to both the high and low bytes of the PC as well as
the instruction memory access must be executed with the
BCP CPU idle Four accesses by the RP are necessary to
read or write both the high and low bytes of the PC Timing
for a PC access is shown in Figure 4-7(a) and (b) The PC
becomes valid on a Remote Read (a) one T-state after LCL
rises and one T-state before XACK rises AD is in TRI-
STATE while LCL is high for a Remote Write (b) Time in the
Access Phase is two T-states if WAIT is not asserted
Instruction memory (IMEM) is accessed through another in-
ternal path from AD to the I bus shown in Figure 4-8(c)
The memory is accessed first low byte then high byte Low
and high bytes of the 16-bit I bus are alternately accessed
for Remote Reads An 8-bit holding register ILAT retains
the low byte until the high byte is written by the Remote
Processor for the write to IMEM The BCP increments the
PC after the high byte has been accessed
RIC
BIS
7
MS1 0
as shown in Figure 4-5
SS
FIGURE 4-5 Memory Select Bits in RIC
6
FBW
e
5
e
00 After that the RP simply reads or
10 allows access to the low byte of the
LR
4
LW
3
Memory Select Bits
00 - Data Memory
01 - Instruction Memory
10 - PC low byte
11 - PC high byte
ST
2
X
MS1
1
MS0
0
Y
e
11
65
(b) As before the Memory Select bits are first set to instruc-
Figure 4-8(a) shows a Remote Read of Instruction memory
Timing for an IMEM access is shown in Figure 4-8(a) and
tion memory
Memory is the power-up Memory Selection state ) A simple
state machine keeps track of which instruction byte is ex-
pected next low or high byte The state machine powers
up looking for the low instruction byte and every IMEM ac-
cess causes this state machine to switch to the alternate
byte Accesses other than to IMEM will not cause the state
machine to switch to the alternate byte but writing 01 to the
Memory Select bits in RIC (i e MS1 – 0
IMEM) will always force the state machine to the ‘‘low byte
state’’ This way the instruction word boundary can be reset
without resetting the BCP When the BCP is reset the state
machine will also be forced to the ‘‘low byte state ’’
Both the low byte then the high byte can be seen on back
to back remote reads An instruction byte becomes active
on the AD bus one T-state after LCL rises and is valid when
XACK rises This time period will be a minimum of one
T-state but can be extended up to three more T-states by
instruction wait states
MS1 – 0 once for repeated IMEM accesses (Instruction
(b) Remote Write Timing (RAE
FIGURE 4-6 Generic DMEM Access
(a) Remote Read Timing (RAE
MS1 – 0
(Continued)
e
01 It is only necessary to set
e
e
e
01 pointing to
0)
0)
TL F 9336 – 83
TL F 9336 – 84