dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 97

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

5 0 Device Specifications
5 5 SWITCHING CHARACTERISTICS
The following specifications apply for V
T
5 5 1 Definitions
The timing specifications for the BCP are provided in the
following tables and figures The tables consist of five sec-
tions which are the following the timing parameter symbol
the parameter ID
for the parameter and the timing specification for the pa-
rameter Below each table is a figure containing the wave-
forms for the parameters in the table
The parameter symbol is composed of the type of timing
specification and the signal or signals involved Note that
the symbols are unique only within a given table The follow-
ing symbol conventions are used for the type of timing spec-
ification
The parameter ID
parameter to the appropriate timing relationship in the ac-
companying figure The waveforms in the figures are shown
with the CPU clock running full speed ( CCS
case CPU-CLK and CLK-OUT are equivalent If CPU-CLK
2 is selected ( CCS
CLK-OUT is for CLK-OUT to double in frequency The same
is true for waveforms with X1 Note that CLK-OUT is always
running at the crystal frequency and it is the CPU-CLK that
is changing to half speed
The parameter description defines the timing relationship
being specified BCP pin references are capitalized in the
description
Many of the timing specifications are dependent on vari-
ables such as operating frequency and number of pro-
grammed wait states The formula for the parameter allows
an accurate timing specification to be calculated for any
combination of these variables The formula represents the
part of the timing specification that is synchronized to the
internal CPU clock This value is calculated and then added
A
Symbol
t
t
t
t
t
t
t
t
t
W-RD
W
PD
H
SU
ZA
AZ
ACC
T
e
0 C to 70 C
(enable time)
(disable time)
Pulse width specification
Propagation delay specification
Hold time specification
Setup time specification
High impedance to active delay specification
Active to high impedance delay specification
Access time specification
Clock period specification
ID
10
the parameter description the formula
e
is used to cross reference the timing
1) the effect on the waveforms with
Read Low
Parameter
CC
(Continued)
e
e
4 5V to 5 5V
0) For this
(MAX(n
DW
97
Formula
n
IW
to the value specified under the Min or Max column to cre-
ate the minimum or maximum guaranteed timing specifica-
tion for the parameter
The following acronyms are used in the tables
The following table is an example of the format used for the
timing specifications In this example t
pulse width specification for the output pin READ The ID
for locating the parameter in the timing waveforms is 10
The formula for this specification involves data and instruc-
tion memory wait states and the CPU clock period For the
case of 3 data memory wait states and 0 instruction memory
wait states and a CPU clock period of 50 ns the READ low
minimum pulse width would be calculated as
(MAX(3 0
For the case of 1 data memory wait state and 3 instruction
memory wait states and a CPU clock period of 50 ns the
READ low minimum pulse width would be calculated as
(MAX(1 3
To calculate n
n
n
cle
Data Memory Access Cycle is normally 3 T-states if 4TR
e
LOR and WAIT can extend n
LW
LW
b
DMEM refers to data memory
IMEM refers to instruction memory
RIC refers to the Remote Interface Control register
PC refers to the BCP Program Counter
T refers to the CPU clock period in ns
T
clock in ns
T
CPU clock in ns
C refers to the transceiver clock period in ns
n
grammed in DCR
n
grammed in DCR
n
local data memory access
n
access
MAX(A B) means take the greater value of A or B
0 and 4 T-states if 4TR
IW
DW
LW
RW
1)
H
L
(max)
(min)
a
refers to first half pulse width (high time) of the CPU
refers to second half pulse width (low time) of the
is the number of instruction memory wait states pro-
is the number of remote wait states due to a BCP
is the number of CPU wait states due to a remote
1)T
is the number of data memory wait states pro-
b
b
e
e
1)
1)
a
a
a
0
MAX(n
LW
1)T
1)T
the following two equations are needed
a
a
DW
(
(
b
b
b
Min
10)
10)
n
10
IW
e
e
– 1)
e
LW
4T
3T
a
1 Keep in mind that both
Data Memory Access Cy-
b
b
10
10
Max
10
e
e
W-RD
190 ns
140 ns
indicates a
Units
ns