dp8344b National Semiconductor Corporation, dp8344b Datasheet - Page 33

• Manufacturer Part Number: dp8344b
• Description: Biphase Communications Processor?bcp
• Manufacturer: National Semiconductor Corporation

ure 2-18 shows a Four T-state Read of data memory The
2 0 CPU Description
When the Four T-state Read mode is selected ( 4TR
a second TX state is inserted before T2 and the timing of
the read strobe READ is changed such that READ falls
one-half T-state after the beginning of the second TX Fig-
extra half T-state before READ falls allows more time for the
BCP to TRI-STATE the AD lines before the memory circuit
begins driving those lines
The four T-state program control instruction timing is shown
in Figure 2-19 The instruction has two TX states inserted
between T1 and T2 ICLK rises at the beginning of T1 and
falls at the end of the second TX The next instruction ad-
dress becomes valid halfway through the second TX The
four T-state two word program control instruction timing is
the same as two consecutive two T-state instructions and is
shown in Figure 2-20
This timing describes the minimum cycle time required by
each type of instruction The BCP can be slowed down by
FIGURE 2-18 Four T-state Data Memory Read Instruction 4TR
(Continued)
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changing the number of wait states selected in the Device
Control Register
up to three instruction memory wait states (instruction wait
states) and seven data memory wait states (data wait
states) Instruction wait states affect all instruction types
while data wait states affect only data memory access in-
structions Bits three and four in DCR control the number
of instruction wait states and bits zero one and two are
used to select the number of data wait states The relation-
ships between the control bits and the number of wait states
selected are shown in Table 2-24 and Table 2-25 The BCP
is configured with three instruction wait states and seven
data wait states and 4TR set to zero after reset A write
to DCR 4 3
states takes effect on the following instruction if that instruc-
tion is a three T-state or four T-state program control in-
struction For the other instruction types the new number of
instruction wait states will take effect on the instruction fol-
to change the number of instruction wait
DCR
The BCP can be programmed for
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1
TL F 9336 – H5