adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 10

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

Table 5. Pin Function Descriptions
Pin No.
1, 13, 26,
38, 51,
62, 76,
88
2, 14, 27,
39, 52,
63, 77,
89
3
4
5
Mnemonic
DGND
IOVDD
BCLK3
LRCLK3
SDATA_IN2
ADDR1/CDATA
NOTES
1. THE EXPOSED PAD DOES NOT HAVE AN INTERNAL ELECTRICAL CONNECTION TO THE INTEGRATED CIRCUIT,
BUT SHOULD BE CONNECTED TO THE GROUND PLANE OF THE PCB FOR PROPER HEAT DISSIPATION.
SDATA_IN2
SDATA_IN1
SDATA_IN0
SDA/COUT
SCL/CCLK
CLATCH
LRCLK3
LRCLK2
LRCLK1
LRCLK0
ADDR0
BCLK3
BCLK2
BCLK1
BCLK0
IOVDD
IOVDD
DGND
DGND
DVDD
MP10
MP11
MP9
MP8
Type
PWR
PWR
D_IO
D_IO
D_IN
10
12
13
14
16
17
19
20
22
23
25
11
15
18
21
24
1
4
6
9
2
3
5
7
8
1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
PIN 1
99
Description
Digital Ground. The AGND, DGND, and PGND pins should be tied directly together in a common
ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor.
Input and Output Supply. The voltage on this pin sets the highest input voltage that should be
present on the digital input pins. This pin is also the supply for the digital output signals on the
clock, data, control port, and MP pins. IOVDD should always be set to 3.3 V. The current draw of this
pin is variable because it is dependent on the loads of the digital outputs.
Bit Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on
if the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin can be
left disconnected.
Frame Clock, Input/Output Clock Domain 3. This pin is bidirectional, with the direction depending on
if the Input/Output Clock Domain 3 is set up as a master or slave. When not used, this pin can be
left disconnected.
Serial Data Port 2 Input. When not used, this pin can be left disconnected.
98
97
96
95
ADAU1442/ADAU1445/ADAU1446
94
93
92
Figure 7. Pin Configuration
Rev. PrA | Page 10 of 92
91
90
(Not to Scale)
TOP VIEW
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DVDD
BCLK8
SDATA_IN8
SDATA_OUT5
LRCLK9
BCLK9
SDATA_OUT6
LRCLK10
BCLK10
SDATA_OUT7
LRCLK11
BCLK11
IOVDD
DGND
SDATA_OUT8
PLL0
PLL1
MP0/ADC0
MP1/ADC1
MP2/ADC2
MP3/ADC3
RESET
CLKOUT
IOVDD
DGND