adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 52

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

ASRC Input Select Pairs[7:0] Registers
(Address 0xE080 to Address 0xE087)
The inputs to each of the eight ASRCs can come from any stereo
pair from either the serial input channels or the DSP core.
In the case of the ADAU1442, each stereo input to the ASRCs
can receive a separate data input, and all of these sources may
be asynchronous to one another.
In the case of the ADAU1445, each stereo input to the ASRCs
can receive a separate data input; however, all inputs to
Table 31. Bit Descriptions of ASRC Input Select Pairs[7:0] Registers
Bit Position
[15:6]
[5:0]
Description
Reserved
ASRC input data selector
000000 = Serial Input Pair 0 (Channel 0, Channel 1)
000001 = Serial Input Pair 1 (Channel 2, Channel 3)
000010 = Serial Input Pair 2 (Channel 4, Channel 5)
000011 = Serial Input Pair 3 (Channel 6, Channel 7)
000100 = Serial Input Pair 4 (Channel 8, Channel 9)
000101 = Serial Input Pair 5 (Channel 10, Channel 11)
000110 = Serial Input Pair 6 (Channel 12, Channel 13)
000111 = Serial Input Pair 7 (Channel 14, Channel 15)
001000 = Serial Input Pair 8 (Channel 16, Channel 17)
001001 = Serial Input Pair 9 (Channel 18, Channel 19)
001010 = Serial Input Pair 10 (Channel 20, Channel 21)
001011 = Serial Input Pair 11 (Channel 22, Channel 23)
010000 = DSP-to-ASRC Pair 0 (Channel 0, Channel 1)
010001 = DSP-to-ASRC Pair 1 (Channel 2, Channel 3)
010010 = DSP-to-ASRC Pair 2 (Channel 4, Channel 5)
010011 = DSP-to-ASRC Pair 3 (Channel 6, Channel 7)
010100 = DSP-to-ASRC Pair 4 (Channel 8, Channel 9)
010101 = DSP-to-ASRC Pair 5 (Channel 10, Channel 11)
010110 = DSP-to-ASRC Pair 6 (Channel 12, Channel 13)
010111 = DSP-to-ASRC Pair 7 (Channel 14, Channel 15)
100000 = S/PDIF Receiver Pair 0 (Channel 0, Channel 1)
111111 = no data
Rev. PrA | Page 52 of 92
ASRCs[3:0] must be synchronous to each other, and all inputs
to ASRCs[7:4] must be synchronous to each other. The first
group of ASRCs (ASRCs[3:0]) takes its input rate from the
ASRC 0 input, and the second group of ASRCs (ASRCs[7:4])
takes its input rate from ASRC 4 input.
In the case of the ADAU1446, which contains no ASRCs, these
registers do not affect system operation in any way and can be
ignored.
Default
111111