adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 24

• Manufacturer Part Number: adau1442
• Description: Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
• Manufacturer: Analog Devices, Inc.

CONTROL PORT
Overview
The ADAU144x can operate in one of three control modes: I
control mode, SPI control mode, or self-boot mode (no external
controller).
The ADAU144x has both a 4-wire SPI control port and a 2-wire
I
registers. When the SELFBOOT pin is low at power-up, the chip
defaults to I
pulling Pin CLATCH low three times. When the SELFBOOT pin is
set high at power-up, the ADAU144x loads its program, parameters,
and register settings from an external EEPROM at startup.
The control port is capable of full read and write operations for
all memories and registers, except for those that are read only.
Most signal processing parameters are controlled by writing
new values to the parameter RAM using the control port. Other
functions, such as mute and input/output mode control, are
programmed by writing to the registers.
All addresses can be accessed in either a single-word mode or a
burst mode. A control word consists of the chip address, the
register/RAM subaddress, and the data to be written. The
number of bytes per word depends on the type of data that is
being written.
The first byte (Byte 0) of a control word contains the 7-bit chip
address plus the R/ W bit. The next two bytes (Byte 1 and
Byte 2) together form the subaddress of the memory or register
location within the ADAU144x. This subaddress needs to be
two bytes because the memory locations within the ADAU144x
are directly addressable, and their sizes exceed the range of
single-byte addressing. All subsequent bytes (starting with
Byte 3) contain the data, such as control port data, program
data, or parameter data. The exact formats for specific types of
writes are shown in Figure 13 and Figure 19.
The ADAU144x has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks on the output. In cases where large blocks of data need to
be downloaded, the output of the DSP core can be halted, new
data can be loaded, and then the output of the DSP core can be
restarted. This is typically done during the booting sequence at
startup or when loading a new program into RAM. In cases
where only a few parameters need to be changed, they can be
loaded without halting the program. A software-based safeload
mechanism is included for this purpose, and it can be used to
buffer a full set of parameters (for example, the five coefficients
of a biquad) and then transfer these parameters into the active
program within one audio frame.
The control port pins are multifunctional according to the
mode in which the part is operating. Table 14 details these
functions.
2
C bus control port. Each can be used to set the RAMs and
2
C mode but can be put into SPI control mode by
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2
C
I
The ADAU144x supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU144x and the system I
In I
means that it cannot initiate a data transfer.
Each slave device is recognized by a unique address. The
address bit sequence is shown in Table 11. The ADAU144x has
eight possible slave addresses: four for writing operations and
four for reading. These are unique addresses for the device and
are illustrated in Table 12.
Users can communicate with these addresses by using the USBi
communication channel list in the hardware configuration tab
of SigmaStudio. The LSB of the byte sets either a read or write
operation; Logic Level 1 corresponds to a read operation, and
Logic Level 0 corresponds to a write operation. Address Bit 5 and
Address Bit 6 are set by tying the ADDRx pins of the ADAU144x to
Logic Level 0 or Logic Level 1. Both SDA and SCL should have
pull-up resistors on the lines connected to them (a standard value is
2.0 kΩ, but this can be changed depending on the capacitive load
on the line). The voltage on these signal lines should not be greater
than the voltage of IOVDD (3.3 V).
Table 11. ADAU144x Address Bit Sequence
Bit 0
0
Table 12. ADAU144x I
ADDR1
0
0
0
0
1
1
1
1
1
Addressing
Initially, all devices on the I
the devices monitor the SDA and SCL lines for a start condition
and the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address or
an address and data stream follows. All devices on the bus respond
to the start condition and shift the next eight bits (7-bit address
+ R/ W bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition. The R/ W bit determines the direction of the
2
0 = write, 1 = read.
C Port
2
C mode, the ADAU144x is always a slave on the bus, which
Bit 1
1
ADDR0
0
0
1
1
0
0
1
1
Bit 2
1
Read/Write
0
1
0
1
0
1
0
1
Bit 3
1
2
C Slave Addresses
2
2
C bus are in an idle state, in which
C master initiates a data transfer by
Bit 4
0
1
Slave Address
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
Bit 5
ADDR1
2
C master controller.
2
C compatible)
Bit 6
ADDR0
Bit 7
R/W