adau1442 Analog Devices, Inc., adau1442 Datasheet - Page 58

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adau1442

Manufacturer Part Number
adau1442
Description
Sigmadsp Digital Audio Processor With Flexible Audio Routing Matrix
Manufacturer
Analog Devices, Inc.
Datasheet

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In the case of the ADAU1446, setting these registers does not
affect system operation in any way.
ASRC[7:4] Mute Ramp Disable Register (Address 0xE143)
Table 38. Bit Descriptions of Register 0xE143
Bit
Position
[15:1]
[0]
Description
Reserved
ASRC[7:4] (Channels[15:8]) mute ramp
disable
0 = enable ramp
1 = disable ramp
Default
0
Rev. PrA | Page 58 of 92
This single-bit register controls the behavior of ASRCs[7:4]
(Channels[15:8]) on a loss of lock. When Bit 0 is set to the
default (0), ASRCs[7:4] (Channels[15:8]) mute with a volume
ramp. When Bit 0 is set to 1, ASRCs[7:4] mute abruptly. In
addition, setting this bit to 1 ignores the ASRC mute bits
(Bits[3:0]) in Register 0xE141 (see the ASRC[7:4] Lock Status
and Mute Register (Address 0xE141) section), so a mute only
occurs on a loss of lock.
In the case of the ADAU1446, setting this register does not
affect system operation in any way.

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